# Is it bad to run traces directly over each other on separate layers?

A bit new to PCB design, I have to run two traces between two pins, and the best way I can think of is to have one trace go to the bottom layer through a via and then run directly under the top layer trace.

Are there any issues that can come about doing this? They're pretty low power signal traces, but can the traces affect each other through induced fields, or are the top and bottom layers generally isolated?

edit: The traces are running over each other for about 700mils. They're SPI data lines.

• How many layers do you have? What are the risetimes or frequencies of your signsls? Dec 18 '17 at 15:50
• If the signals are low power (they are), low frequency (rough guess: less than 100 MHz) and not very sensitive to external disturbances (like when carrying sensitive signals of a few mV) then sure you can route them on top of each other. Induced fields:usually not an issue but parasitic capacitance can be at high frequency and/or sensitive lines. Best bet: ask the circuit designer. Dec 18 '17 at 15:56
– pipe
Dec 18 '17 at 16:00
• can you simulate the PCB layout? Dec 18 '17 at 16:41

The only answer to the actual question in the title is: Maybe

Is it bad? Not necessarily, but there will be both capacitive and inductive coupling between them. How much depends entirely on the shared length, size, and the distance between the traces.

Assuming these are for example digital signals from a microcontroller at lowish speeds, it is unlikely to be a problem.

Fast signals and analog signals - then you need to tell us the specifics.

At high speeds "crosstalk" may become an issue. "Crosstalk" happens when one signal's electric field couples the signal over to an adjacent trace that mimics the source signal. This can interfere with the signal being passed along the second trace and create false crossings and other noise that cause the receiver to detect errant data. The best way to eliminate this is to have traces running in opposite directions (perpendicularly) on adjacent layers, or have a ground plane between each layer. These methods minimize the coupling between two signal traces. At lower speeds this generally won't be a concern though.

Here is a specific example, with 4 millivolt peak-peak signal of 1million ohm source impedance, driving an Analog-Digital Converter of 10pF input capacitance. The interferer is MCU clock, located 1 millimeter away from the signal trace.

With interference[the screen shoot illustrates this case], the SNR is -22dB (that MCU trash is 12X stronger than the 4milliVolt signal. To compute this, the "Gargoyles" button is checked, also the far-right "I/C" button is checked, and then "Update" button is clicked.

Without interference ("Gargoyles" turned off) SNR is +39dB (signal nearly 100X stronger than the ----- random thermal noise ----- measurement floor.

Thus the presence of Efield interferer caused ---- in this case ---- 60dB change, or 1,000:1 change, in the Signal Noise Ratio.

and here is the (editable; you got here by clicking OFF the global-trace mode and then clicking on the "trace wizard") default dimensions of the trace used as the vulnerable signal trace, the victim of Efield trash injection, modeled in this version as parallel-plate capacitance coupling.

How does SignalChain Explorer work? By modeling the Signal Chain, the tool has access to the NODE IMPEDANCE; when a current (displacement current, arriving from capacitive interference) enters any node, the error voltage is simply Current * Node_Impedance.

In this example, the signalChain has only 1 node available to respond to interference: the point of connection between Sensor Output and the ADC input. The default Efield interferer is the MCU clock, defaulted to 1mm distance from the signal trace, with 100MHz clock rate and 2.5 volt peak-peak voltage.

The sensor has Zout of 1Million ohms. The ADC has 100 ohms Rin and 10pF, a time constant of 1nanosecond and F3dB of 160MHz; the MCU clock energy blasts onto the ADC, attenuated only by the capacitive-division of the two series capacitors: 1) the parallel-plate coupling model used between the two traces (MCU trace and signal chain trace) 2) the node capacitance, dominated by 10pF of the ADC sampling capacitor.

Running traces on two separate layers can be bad because you are introducing parasitic capacitance between the layers.

Source: EDN

You can calculate the capacitance by finding the area that is crossing between the traces and the height between them and the electric relative permeabilty $\epsilon_r$ which is around 4.4 for fr4 PCB material:

Source: Reference Designer

Usually this results in a capacitance that is a few pf's, if that is too much capacitance between nets then run traces on different layers OR use a different layer stackup to ensure there is a ground plane running between signal layers.

So decide if a few pF of capacitance would be detrimental to your design, this usually only applies to high speed designs, another way to avoid this is to have a stackup like this (for a four layer design):

Signal
GND
POWER
Signal