# Moore vs mealy, why the output is delayed in the former?

I am not an engineer (software developer myself) but would like to understand why moore machine output is delayed.

I know that in Moore's machine, output depends only on the state, while in Mealy's machine, it depends on both the current input and the state.

But to me it does not explain why it is said to be delayed (or as one source puts it "the change in the input will manifest on the output in the next status".

But why? If the Moore input is entered, the state changes and the output is generated. So what is this delay?

Moore outputs are synchronous with clock. It changes only with state transition at clock edge. Mealy outputs are asynchronous. They can change immediately with input change, independent of the clock. So we can say moore machine is not as "fast" as mealy.

• And that is what I do not get. If the input is provided, status changes and the output is generated (I believe). So the whole point is that the output might be generated a little bittle earlier than the status changes? – John V Dec 19 '17 at 12:24
• In Moore machine, change in input reflects on the output only when a clock edge comes. But in mealy it is immediately reflected. "Synchronous vs Asynchronous" difference. :-) – Meenie Leis Dec 19 '17 at 12:30

If the Moore input is entered, the state changes and the output is generated. So what is this delay?

In the Moore machine the output is dependent only on current state, and the latter to the input prior to the next clock transition. Therefore the output corresponding to the current input will show up only after a (positive-edge) clock transition is made. Therefore the output has one clock cycle delay corresponding to the Mealy state machine.

To put it more, the output of a single-input Moore machine can be written as Z(x=n)=f(flip-flops' state(n)), where flip-flops' state(n) is a function of x(n-1) and other parameters. Since the output Z(n) for x=n corresponds to flip-flops' state(n), and the current flip-flops' state is n-1, we have to wait for one clock cycle so that the output corresponding to the time n appears, which is when flip-flops' state has changed to n.

• But if I understand it correctly, then for both machines, the provided input leads to a change of status and generation of an output. With Moore, it will be just a bit delayed but from high level perspective (seconds), it is the same? – John V Dec 19 '17 at 12:27
• If your clock period is also in the seconds range, they are not the same. – Brian Drummond Dec 19 '17 at 14:57

The additional delay in a Moore SM is simply the remaining fraction of a clock cycle after the input arrives, and before the next active clock edge.

Whether or not this is significant depends on the context of the design.

One feature of the Mealy machine passing inputs directly to the outputs is that it may produce output signals with durations much less than a clock cycle, called glitches or runt pulses. This may cause mis-operation of logic depending on the state machine.

The Moore type (and also the preferred single-process style of state machine in VHDL) produces clean output pulses one or a multiple of a clock period in length.

Both styles of state machine are vulnerable to mis-operation given inputs arriving too close to a clock edge, so using either type, you should synchronise inputs to the clock before passing them to the state machine.