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I understand that in I2C, SCL and SDA lines use pull-up resistors and the pin drivers are open collector NPN devices which can drive pins to ground. This gives I2C an advantage that the same bus now can be shared with multiple slaves, and even if two or more slaves accidentally try to drive the bus at the same time it won't cause any damage to the system.

But this can also be done using PNP open drain drivers and pull-down resistors on SDA and SCL lines. Things like clock-stretching and multi-master arbitration can be achieved with this too.

Does the current implementation of I2C protocol gives any benefits over the above suggested alternative implementation?

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    \$\begingroup\$ open collector transistors seemed to be in the majority in ICs in the 80s. \$\endgroup\$ – PlasmaHH Dec 19 '17 at 13:42
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    \$\begingroup\$ @PlasmaHH I think the reason was NPN (as far as I remember vaguely) has more current capacity per area due to higher electron mobility in the substrate, so it's easier to build "strong" output stages with that. \$\endgroup\$ – Marcus Müller Dec 19 '17 at 13:46
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    \$\begingroup\$ @MarcusMüller Indeed, that was (and still is) true. NPNs and NMOS Fets are "stronger" when given the same size. In CMOS a factor 2 to 3 is typical. For PNP vs NPN it depends on the fabrication process but almost always PNPs are far more difficult and complex than the NPNs. Also starting with a P-doped substrate (as most processes do) emphasizes this (better NPNs). \$\endgroup\$ – Bimpelrekkie Dec 19 '17 at 13:52
  • \$\begingroup\$ @Bimpelrekkie I remember a factor of 2.3 from my solid state physics class to this date :-) \$\endgroup\$ – winny Dec 19 '17 at 19:02
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    \$\begingroup\$ If the existing I2C bus is accidentally shorted to ground for any reason then you'll only draw pull-up resistor current. With the complementary arrangement of active-high drivers and pull-down resistors, you'd damage simple drivers from the I2C starting years. When going between boards, shorting to chassis is a consideration. But it's just one of many reasons for going drive-low pull-high, the rest of which others have answered below. \$\endgroup\$ – TonyM Dec 19 '17 at 22:07
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Electrically it makes sense because ground is the one common connection to all devices on a IIC bus. That's a lot less of a restriction than forcing power to be the common connection to all IIC devices, as would be required if the lines were driven high and floated low via pulldowns.

Note that IIC devices don't all need to be powered from the same net or the same voltage. This would not be true if both bus lines had to be driven to the single common power voltage.

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    \$\begingroup\$ Not my downvote, and you must have as many years I2C experience as me, so my point here is likely a misunderstanding, but: "IIC devices don't all need to be powered from [...] the same voltage" might be seen as implying that 5V-powered and 3V-powered I2C devices (for example) could share the same I2C bus, without any additional components or precautions (since you didn't mention level-translators). And of course they can't do that, since each device's I2C logic thresholds are now referenced to their own Vcc. Perhaps the lack of an explicit mention of level-translators caused the downvote? \$\endgroup\$ – SamGibson Dec 19 '17 at 15:19
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    \$\begingroup\$ Depending upon the pull-ups and I/O pins used, I2C-style communications can operate smoothly between 5V and 3.3V devices. Using 10K pull-ups to 5V, for example, would allow 3.3V devices to be used if they have 5V-tolerant unclamped inputs or if they can tolerate 150uA into their protection diodes. And using pullups to 3.3V will work, at least at slower speeds, for interfacing with 5V devices that have an input high threshold which is 2.5V or less. \$\endgroup\$ – supercat Dec 19 '17 at 15:31
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    \$\begingroup\$ @Sam: Actually 5 V and 3.3 V IIC devices can be on the same IIC bus. Devices with fixed voltage levels regardless of their supply voltage are specifically mentioned and sanctioned in the IIC spec. \$\endgroup\$ – Olin Lathrop Dec 19 '17 at 15:33
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    \$\begingroup\$ In the old document "The I2C-bus and how to use it" by Philips, section 10.0 mentions the fixed input thresholds of the early (typically NMOS) 5V I2C devices. It then says: "I2C-bus devices with input levels related to VDD must have one common supply line to which the pull-up resistor is also connected" (my bold). @supercat - you mentioned: "5V devices that have an input high threshold which is 2.5V or less" Can you help me by giving an example of such a device? Reading old I2C docs, I can only find mentions of a fixed 3V I2C Vih minimum, for those old 5V devices. Thanks. \$\endgroup\$ – SamGibson Dec 19 '17 at 16:33
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    \$\begingroup\$ @SamGibson: Devices with input levels related to VDD may need to operate from voltages which are within a certain range of each other. How close they must be depends upon how the voltages are related to VDD. The Microchip data sheet for the PIC16F877 (a 5V part selected arbitrarily) lists V(IH) for its normal pins as 0.25VDD+0.8V, though for its Schmitt Trigger inputs it would be much higher. At VDD=5.2V, a normal input would have a specified V(IH) of 2.1 volts; I didn't see a spec for the hardware I2C V(IH), though the typical performance graph suggests it's between normal and ST inputs. \$\endgroup\$ – supercat Dec 19 '17 at 17:37
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In the good old days, TTL drivers were much better at pulling a signal down than pulling it up. Therefore, protocols like I2C, but also interrupt lines, reset, and others, were all implemented using a pull-up with distributed pull-down.

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    \$\begingroup\$ In the better modern days, the same still holds true as it is an intrinsic property of the semiconductors. Today it just doesn't cost as much to get a beefier pull up transistor to handle the same current. \$\endgroup\$ – Arsenal Dec 19 '17 at 13:50
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    \$\begingroup\$ I was told that with CMOS it is also much easier to get close to the power rail voltage. Another 'issue' where TTL was struggling. (Maybe we should count ourselves lucky for that as it allowed 3V3 CMOS to interface with TTL) \$\endgroup\$ – Oldfart Dec 19 '17 at 14:06
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It's easier to use ground as a common reference among subsystems that might have varying supply voltages. If you use PNP transistors to pull up to a supply voltage, all subsystems would have to be connected to the same supply.

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Good answers abound here, but there is also another reason.

If the quiescent state of the bus is at ground, there is no way to tell if the bus is connected or just hanging in space.

It is normal for the pull-up to be located at the master device. Slaves usually do not have a pull-up. This is because the pull-down current that would be required to assert a low level would increase with the number of devices connected to the bus.

A slave, when plugged into the bus, can then detect that the line is pulled-high (Assuming it is not being used) and know that the bus is actually there and quiet. That would not be the case with a ground biased bus.

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  • \$\begingroup\$ In order to detect the bus being pulled high, a slave must pull it low in the first place. I'm not sure why a similar procedure would not be possible with the opposite polarity. \$\endgroup\$ – Dmitry Grigoryev Dec 21 '17 at 10:27
  • \$\begingroup\$ @DmitryGrigoryev why would it need to pull something that is already high low? \$\endgroup\$ – Trevor_G Dec 21 '17 at 13:08
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If I understand the question correctly one aspect is:

  • Why do you use pull-up resistors and NPN transistors instead of pull-down resistors and PNP transistors?

First of all you should note that you don't use bipolar transistors (NPN, PNP) but MOSFETs (which exist in four different variants).

Devices using the "pull-up and NPN" variant use a n-channel enhancement MOSFET. Because the source of this MOSFET is connected to ground the gate-source voltage (controlling the current flow) is equal to the voltage between gate and ground. So the MOSFET can be controlled using a voltage between 0 and Vdd.

There would be three possibilities to implement the "pull-down and PNP" variant:

  • Using a p-channel enhancement MOSFET

    On an NMOS or CMOS IC p-channel MOSFETs with comparable characteristics (resistance etc.) require more space than n-channel MOSFETS.

    In microelectronics space is money so p-channel MOSFETs avoided if possible.

  • Using an n-channel enhancement MOSFET

    This would require the output of the logic circuit driving the transistor to have a "LOW" voltage of the supply voltage (e.g. +5V) and a "HIGH" voltage above the supply voltage (e.g. +10V when the rest of the circuit is supplied with +5V).

    The reason: The source-ground voltage will be Vdd when the MOSFET is conducting. The gate-source voltage must be positive so the voltage between gate and ground must even be higher.

    You would need two voltage supplies - and a circuit shifting the output of the logic circuit from 0...+5V to +5V...+10V ...

  • Using an n-channel depletion MOSFET

    Unfortunately I can't tell you much about this solution. However I found some page using Google saying that depletion MOSFETs are more difficult to produce than enhancement MOSFETs and they are avoided for this reason.

    I know from power electronics (not microelectronics) that the "two power-supply" variant described above is even preferred over depletion MOSFETs. (But I cannot tell you why.)

    EDIT Using n-channel depletion MOSFETs you would probably need a negative voltage (e.g. -5V) so you would also need two supply voltages...

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There is also one more added benefit for having common ground and pull-up data lines (over having common VCC and pull-down):

Even if the original intention was to connect devices on the same PCB at span of few inches only, it was successful enought so now is not uncommon to have the lines long couple of feets and connecting "devices" which could be computers or something of equal complexity, with some devices having its own power sources (of different quality, say you connect something wall-plug powered with something battery powered). It is better, if connection works "at least good" even in not ideal and out-of-spec conditions.

And lot of such connected devices may be somehow connected also by other means, then only I2C communication. Usually when connecting devices together you connect it with common ground - sometimes as part of other functions, sometimes just because it is mounted on metal case and the devices are ground-connected with the case too (or with common cooler or something like that) or there may be shielded cable with grounded shield inside - which also connects the grounds.

If you also directly connect power lines (VCC) of such devices, you will get problems when those lines would be on different voltage naturally (sure, it may say 5V here and there, but depending on the construction and part tolerancies of power sources it could be also 4.9V or 5.2V or even changing, if it is battery powered and sometimes running some motors, making the power drop and rise over time).

In such case there is effectively short circuit betwenn those power sources of part a Volt and depending on the sources (and resistance of the ways) there could flow relatively high currents resulting not only in energy waste and heat rising, but maybe even in damaging (or shortening life) of some of those sources. Which is not good.

Having common ground and pull-ups avoids such problems - ground is ground and pullup resistors allow for only really small cross current even if the VCC differs a lot over the devices.

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    \$\begingroup\$ This is essentially the same as Dave Tweed's answer. \$\endgroup\$ – Janka Dec 21 '17 at 4:06
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You don't have to send so much power through the chip, if it's pull up.

Because the chip doesn't drive anything, it's just creating a short to bring the bus to 0, and doing an open to bring it to 1.

If it was pull down, you'd have to send power through the chip to drive the bus to 1. If the bus happens to be an accidental short, that might be a lot of power you drive through that chip to try to push it up to 1.

Disclaimer: I'm a pretty lousy EE at this point.

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    \$\begingroup\$ Welcome to EE.SE. "You don't have to send so much power through the chip, if it's pull up." If the pull-up and pull-down resistors are the same size then the currents will be the same. Pull-up will require current to be sourced from the driven chip and sunk in the driving chip. Pull-down will require current to be sourced from the driving chip and sunk by the driven chip. An accidental short could be to V+ or ground. \$\endgroup\$ – Transistor Dec 21 '17 at 7:10

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