as far as I know, register (e.g., reg reg1) and register file (e.g., reg [3:0] reg2)
can be used in the always block whether it is a sequential (i.e., always @(posedge clk)) or combinational (i.e., always @*).
However, only when they are used in sequential always block, Flip-flops are inferred.
I think it's because register and register file in combinational always block are assigned continuously, so memory may not necessary.
However, I don't know why Verilog allows using register and register-files inside the always @* block which is a combinational circuit.
Is it because to enable RT level description such as if statement, case statement, etc in combinational logic?
The name 'reg' confuses me because its name implies the storage (FF), but it acts like a just wire inside the always @* block.
It seems that the 'reg' works as expected as a storage only inside the sequential always block.
Even though assign keyword allows a value to be assigned to a wire variable, is there any other reason that the Verilog allows register and register files to be used inside always @* block as a wire?
To me, a register and register file are just declared as a reg type in combinational always block to be used at LHS of assignment, but act as a wire type variable.
I appreciate any help.