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as far as I know, register (e.g., reg reg1) and register file (e.g., reg [3:0] reg2)

can be used in the always block whether it is a sequential (i.e., always @(posedge clk)) or combinational (i.e., always @*).

However, only when they are used in sequential always block, Flip-flops are inferred.

I think it's because register and register file in combinational always block are assigned continuously, so memory may not necessary.

However, I don't know why Verilog allows using register and register-files inside the always @* block which is a combinational circuit.

Is it because to enable RT level description such as if statement, case statement, etc in combinational logic?

The name 'reg' confuses me because its name implies the storage (FF), but it acts like a just wire inside the always @* block.

It seems that the 'reg' works as expected as a storage only inside the sequential always block.

Even though assign keyword allows a value to be assigned to a wire variable, is there any other reason that the Verilog allows register and register files to be used inside always @* block as a wire?

To me, a register and register file are just declared as a reg type in combinational always block to be used at LHS of assignment, but act as a wire type variable.

I appreciate any help.

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    \$\begingroup\$ Related SO Question. \$\endgroup\$ – Tom Carpenter Dec 19 '17 at 17:22
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    \$\begingroup\$ Ignore the Reg and Wire names. They're language constructs and are useless for predicting what Synthesis will do with your code. A Reg is called that because during simulation it acts as a variable between time steps, but in your actual circuit it can be combinational or a flip flop, as you've observed. \$\endgroup\$ – jalalipop Dec 19 '17 at 17:25
  • \$\begingroup\$ They are confusing. The reg and wire distinction where to ease the implementation of the simulator. Best is to start using System Verilog which does away with the concept and use the type 'logic' instead. But if I recall this question has been asked already several times. stackoverflow.com/questions/13282066/… \$\endgroup\$ – Oldfart Dec 19 '17 at 17:31
  • \$\begingroup\$ @user3535598 Hi, thanks for a comment. Out of curiosity, how the System Verilog is different from the Verilog? Is there any other motivation (including type) to develop System Verilog? \$\endgroup\$ – JaeHyuk Lee Dec 20 '17 at 3:23
  • \$\begingroup\$ @jalalipop Thanks for a clear answer. I have one further question about this topic. Then which syntax or keyword determines what will be the synthesized circuit for the reg? Is it a sensitivity list such as @* or @(posedge clk) ? \$\endgroup\$ – JaeHyuk Lee Dec 20 '17 at 3:25
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However, I don't know why Verilog allows using register and register-files inside the always @* block which is a combinational circuit.

Because designating a signal as reg or wire has nothing to do with whether it is implemented as the output of a register or a combinatorial circuit. It only relates to whether the signal can be assigned to by a procedural assignment (assignment in an initial or always block) or by a continuous assignment (assignment by an assign or instance output).

Reg signals can be assigned to in procedural blocks. Wire signals can be assigned by continuous assignment. That is absolutely all the different signal types mean, and this is simply something you have to get used to when working in Verilog.

The names seem to imply a different meaning because Verilog was originally intended to be a tool for modeling hardware that was designed by other tools rather than a tool to synthesize new designs, and so using it for synthesis has a few warts that reflect the inherent kluginess of doing that.

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  • \$\begingroup\$ "initial or always block or by an assign" - a.k.a. Procedural assignment (for reg) vs. Continuous assignment (for wire). \$\endgroup\$ – Tom Carpenter Dec 19 '17 at 17:36
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    \$\begingroup\$ @TomCarpenter, thanks, I knew there were names for those things, just didn't remember them off the top of my head or find them with some quick searching. Edited now. \$\endgroup\$ – The Photon Dec 19 '17 at 17:41
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The Verilog 1364-2001 LRM changed the terminology so that reg is actually a data type of a variable. Wires represent a sustained signal that is driven by a continuous assignment. A synthesis tool recognizes the pattern of how you use a variable, and determines whether the variable becomes combinational logic, a latch, or a FF.

SystemVerilog replaces the keyword reg with logic to avoid this confusion. It also adds constructs like always_ff so you can indicate the intent of your always block. See http://go.mentor.com/wire-vs-reg

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  • \$\begingroup\$ Thanks for a nice blog post. It was really helpful to understand this issue. However, could you let me know what motivates a development of the system-verilog? I would like to know which problems or issues are dealt with in the system-verilog, which may not be solvable in the Verilog. \$\endgroup\$ – JaeHyuk Lee Dec 20 '17 at 3:38
  • \$\begingroup\$ See quora.com/… \$\endgroup\$ – dave_59 Dec 20 '17 at 6:25
  • \$\begingroup\$ I appreciate it. It helps me a lot :D. \$\endgroup\$ – JaeHyuk Lee Dec 20 '17 at 8:09

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