# PLL - why compare phases not frequencies

I have a question about PLL's. The aim of PLL is to get two signals with the same frequencies (there can be a shift in phases, as I understand). So, in this case, why do you use a phase detector to compare phases, and NOT just compare frequencies?

thank you

## 4 Answers

In most cases, the best way to tell if the frequency of the feedback waveform precisely matches the frequency of reference waveform is to observe whether the two waveforms maintain a fixed phase relationship. If the frequency of the feedback waveform is slightly higher than that of the reference wave, its phase will to lead that of the reference wave form by an increasing amount each cycle. Likewise if its frequency is lower than the reference, its phase will lag each cycle. If the reference waveform is reasonably stable, trying to maintain a phase lock will yield a very stable frequency lock.

There are times when maintaining a phase lock is difficult or counter-productive, such as if one needs to generate a stable frequency whose long-term average matches that of a "warbling" reference. In that case, the fact that a frequency-locked loop wouldn't track the reference frequency as tightly as a phase-locked loop would not be a disadvantage, since the whole purpose of the loop in that case would be to avoid having the warbling in the reference passed through to the output. In general, though, the tighter response of phase-locked loops is preferable to the looser response of frequency-locked loops.

From a more theoretical angle, frequency is the time derivative of phase. Equivalently, phase is the time integral of frequency. So, when a phase detector is used to control frequency via a VCO, there is an integration around the loop. Or, roughly speaking, a low-pass filtering effect.

As supercat points out, the advantage gained is the rejection of "warbling" or even glitches in the reference.

Many years ago, with a freshly minted BEE, I used a PLL to solve a problem where glitches on the backplane clock, due to, for example, hot plugging cards, (this was a digital loop carrier), caused a particularly sensitive card to "lock up", dropping any active call in progress. The PLL rejected the glitches, producing a stable clock for the line card, that, on average, was frequency locked to the backplane clock.

• I can't think of any frequency-locked loops that are more responsive than phase-locked loops. You are correct that the phase is an integral of frequency, but in a typical PID loop the integrator can "wind up" by a significant amount. By contrast, every time a frequency difference is integrated up to a 180-degree phase difference, the phase-vs-frequency response gets inverted. Though I guess that even if one used a counting circuit which could keep track of "phase differences" beyond 180 (or even 360) degrees one could still call such a device a "phase-locked loop". – supercat Jun 27 '12 at 15:15

I think the main reason is that phase can be measured instantaneously in almost zero time, whereas frequency as in Type II phase detectors built into many PLL libraries and PLL chips requires at least one clock cycle. and if using data, the frequency of the signal may not be easy to extract. Also the presence of glitches causes errors.

The reality is that F detect gives faster capture time due to lack of positive feedback when a cycle skips to become positive feedback for Type I phase detectors such as exclusive OR gates or diode or transistor multiplier phase mixers. but these are more immune to glitches and ignore false transitions.

Edge sensitive detectors be they phase or cycle count or frequency detect are not immune to glitches and not a good match for noisy input signals but very useful for PLL frequency scaling with wide range input frequency error for clock synthesis where analog or Type I phase detectors have more difficulty in wide capture range without increasing bandwidth and gain of loop.

My favorite PLL was to capture noisy data on a TV unused vertical blanking interval (VBI) The data was simple 4Mb/s NRZ for one line of data every field. or 1/120th of a sec for NTSC. The VCXO was converted to a sawtooth signal and the data was analog broadcast where noise could be present. The data was filtered to be raised cosine to eliminate ISI and differentiated to product one shot pulses which would sample the phase of the Sawtooth signal and then hold until the next bit transition. It was stable enough to stay in sync from field to field but could correct phase error within 1%. We used it to cyclically broadcast executeable games for TRS-80's VIC-20's in the early 80'S so that it appeared to be a 2 way modem that was only a server sending all the games to be selected quickly( small files back then)

The Phase detector signal using S&H circuit always produces an error signal that is the duplicate of the signal being sampled... in my case a sharp Sawtooth signal. At zero phase error. the data edges lined up with the middle of the Sawtooth.

From mathematical point of view phase detectors don't compare the phases of signals. Usually phase detectors produce non-linear functions (e.g. sin, sawtooth, bunch of pulses) which in some approximation depends only on phase difference between two signals. Complicated non-linear dynamics of the hole system (VCO + phase detector + filter) forces phase-locked loop to synchronize frequency of the VCO to the input frequency. Different modification of PLLs are used to improve performance characteristics (Hold-in, pull-in, and lock-in ranges of PLL-based circuits: rigorous mathematical definitions and limitations of classical theory.) to synchronize frequencies faster and in a more robust way. One of the most popular phase detectors is Phase Frequecny Detector (PFD) is designed to use frequency difference of the signals to improve these characteristics. Good mathematical overview of analog PLL models is given in Phase-Locked loop: nonlinear models and limitations of the classical theory