Using negative voltage will increase turn-on delay time not the actual turn-on rise time. It will decrease turn-off delay time as there will be a higher voltage difference to pull the gate voltage below the threshold.
Consider a 2n7002: Cgs = 4.5e-11 F & treating as a classic capacitance with a 100R gate resistor:
The time to reach the gate threshold for turn-on is longer BUT it is quicker for turn-off.
The benefits are increase resilience to parasitic turn-on due to the miller capacitor during switching transients. Think of it like this, switching a FET is all about moving charge onto the gate-source & off. Now this could occur due to your gate-drive but it could also occur due to parasitic.
When you consider Q = CV & the \$\Delta V\$ is 2.5V for a 0:15V drive and 17.5V for a -15:15V drive, it can be seen the bipolar driver is more resisliant to charge injection, be it due to poor gate-drive design (low drive, high impedance), poor layout or high power/high speed applications.
Consider the small signal capacitance model of a FET & consider a 0V off gatedrive with a 1kR gate resistor.
A very high gate resistor and a very sharp supply pertubation to make the point
With a 0:15V gatedrive there is enough charge being coupled in to potentially take the gate-source voltage of one or both FET's to its threshold voltage
With a -15:15V drive the coupling still occurs BUT now the gate voltage doesn't rise enough to potentially start conduction.