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I make a sample and hold (IC design),and it is combined with transmission gate and a 550fF capacitor,and my classmate told me that my capacitor is too small,almost the same as the parasitic capacitance,and also told me it may have some problem when post-sim.So i want to ask:

What will it happened when the capacitance is almost the same as parasitic capacitance when doing post-sim ? Because it is design to on-chip,so the value of it cannot be too large.

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    \$\begingroup\$ Are you really talking about 0.55pF? \$\endgroup\$ – PlasmaHH Dec 20 '17 at 12:48
  • \$\begingroup\$ yes! i do use 0.55pF \$\endgroup\$ – Shine Sun Dec 20 '17 at 12:49
  • \$\begingroup\$ But why? I find that unusually low. Are you designing an IC? It might make more sense to exploit miller capacitance there \$\endgroup\$ – PlasmaHH Dec 20 '17 at 12:54
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    \$\begingroup\$ Designing an IC is a whole different beast with tons of more caveats. I suggest you read more papers, if you have to ask that question, I bet there are much more things you missed. I see people talking a lot about using the miller capacitance as the hold capacitance. \$\endgroup\$ – PlasmaHH Dec 20 '17 at 13:04
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    \$\begingroup\$ If your hold capacitance is too low you will likely have too much charge injection to have the S&H accurately follow the input when the switch opens. There are circuit techniques to minimize this error by attempting to cancel the charge injection but it is going to be increasingly difficult for a given accuracy spec as you reduce the hold cap. \$\endgroup\$ – Spehro Pefhany Dec 20 '17 at 13:28
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What will it happened when the capacitance is almost the same as parasitic capacitance when doing post-sim ?

post-sim? You probably mean: post-layout extraction and simulation.

If your sampling capacitor has a value similar to the parasitic capacitance then you have a very strange design. In a "normal" design I would say that 80% of the capacitance should be from the sampling capacitor itself and 20 % or less should be from the parasitics.

If your sampling capacitor has a value similar to the parasitic capacitance then you probably have made your transmission gates too large in relation to the sample and hold capacitance.

Parasitic capacitance isn't always an issue, if the sampling cap. is connected between signal and ground and a parasitic capacitance is in parallel with that, the total sampling capacitance will simply have a larger value.

For other parasitic capacitances there are some techniques to minimize their influence. Should you apply these? No, only if you already know that there will be a problem.

Designing a circuit while trying to compensate for everything and including all kinds of "tricks" will result in a clumsy design. The trick is to know your requirements so that you can make educated decisions about what will be a problem and what will not be a problem.

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