# Register Output Frequency

I am getting confused with the working of the circuit. How will the expanded circuit look like?

Assuming the register is SISO, it will take (32-1) clock edges to get the output. What other information I can use?

How is the adder part working ?

Please help me with this. I am not posting this just to get solution to for my homework. I am preparing for an exam and such problems are repeatedly asked and I am not able to start from any where so I can't show my work. The official answer to the problem is option(A).

• have you spoken to your instructor? Commented Dec 21, 2017 at 5:19
• I don't have one. I am preparing for the exam on my own. Commented Dec 21, 2017 at 5:27
• what kind of a course is it? Commented Dec 21, 2017 at 5:28
• I have completed my grad in EEE. Now, I am preparing for GATE 2018. gate.iitg.ac.in/Syllabi/EE_Electrical-Engineering.pdf Commented Dec 21, 2017 at 5:31

First of all:

The schematics is absolutely not acceptable unless such a notation is typically used in your course/company/school/country/...

If I would have seen such a schematic in an examination I would have complained about this!

(See below for reasons)

The actual question:

Before having a look at the possible answers I tried to guess how the schematic could be meant:

• The circuit contains some "register" which is a 32-bit integer number.
• It has an input which is also a 32-bit number
• And it has a clock input
• On each clock pulse the 32-bit input is added to the "register"
• The output is the high bit (bit 31 with the value 2^31) of the "register"

Indeed in this case the answer is (A) so I think I was guessing correctly.

How to solve this question?

The question is: How often does the upper bit of the "register" go from 0 to 1?

The answer is: As often as the bit goes from 1 to 0. And this happens each time when the "register" overflows.

This is the case when the value $$\2^{32}\$$ has been added to the register. And because each clock cycle $$\M\$$ is added to the register the value $$\2^{32}\$$ is reached after $$\\frac{2^{32}}{M}\$$ clock cycles so the "output frequency" is $$\\frac{F}{\frac{2^{32}}{M}}\$$.

By the way

Even this is only true for $$\M \le 2^{31}\$$!

For $$\M = 2^{32}-1\$$ you'll get the same output frequency as for $$\M = 1\$$ if you define the output frequency as "frequency of the change of the upper bit".

Why is this schematic (and therefore the entire question) not acceptable?

Reason one:

Unless the schematic symbols are explained elsewhere they are non-standard. The adder for example could be understood as XOR gate.

Reason two:

The way the schematics is drawn the output is a 32-bit number, not a binary signal.

But what is the "frequency" of the following 3-bit integer output:

0, 5, 2, 7, 0, 5, 2, 7, 0, 5, 2, 7, ...

Would you say: "1/2 of the clock frequency because the upper bit changes every 2nd clock pulse"?

Or would you say: "1/4 of the clock frequency because the sequence repeats every 4th clock pulse"?

In the second case the output frequency in the original question would be $$\F/{2^{32}}\$$ for every odd value of $$\M\$$!

By upper bit, you mean the rightmost bit of X right?

The "register" seems NOT to be a shift register!

Instead this is only a delay of one clock cycle. You might say: The "register" consists of 32 independent 1-bit shift registers. In one clock cycle 32 bits are read in at 32 inputs and in the next clock cycle you see these 32 bits at the 32 outputs.

The "upper bit" is the bit which represents the digit with the significance 2^31 in the 32-bit integer number. (Typically called the leftmost bit.)

I didn't get this "In the second case the output frequency in the original question ...

...

So, option(A) is valid only for even values of M ?

The problem here is: How to understand the schematics?

The way the schematics is drawn the output is not a single logic signal but the output consists of 32 logic signals.

The question is: What is "the frequency" of a bundle of 32 logic signals?

(Depending on the definition you choose the formula would only work for values of N which are a power of 2; all odd numbers of N would result in the same "frequency"; for even values of N which are not a power of two you would get other frequencies which also do not match "formula A".)

The answer is not: "Answer 'A' is wrong" but the answer is: "Obviously the schematic is not meant the way it is drawn!"

And I 'm not able to get "By the way" part.

Because I assume the schematic is not meant the way it is drawn I have to do some assumption:

If we assume that the "output" signal is the uppermost (leftmost) bit of the 32-bit integer number we find out that formula "A" is correct for $$\M \le 2^{31}\$$.

For each time a signal changes its value from 0 to 1 there also must be a value change from 1 to 0.

If we assume that a signal change of any signal in the circuit can only happen at a clock pulse the maximum possible frequency of any signal in the circuit is $$\F/2\$$.

However for values $$\M > 2^{31}\$$ we get higher frequencies than $$\F/2\$$ when using "formula A".

This means that formula "A" cannot be correct for values $$\M > 2^{31}\$$ if we assume that a signal value can only change at a clock pulse.

• By upper bit, you mean the rightmost bit of X right? And I 'm not able to get "By the way" part. Why it will only be true for M<=2^31 and will be same for 2^32 -1 and 1? Commented Dec 21, 2017 at 11:17
• I didn't get this "In the second case the output frequency in the original question would be F/2^32 for every odd value of M". So, option(A) is valid only for even values of M ? And we generally take msb only right? Commented Dec 21, 2017 at 11:20
• @NikhilKashyap I added some comments at the end of my answer. Commented Dec 21, 2017 at 12:54
• WOW !! How clearly you explained everything @MartinRosenau. I really appreciate your effort. Thanks alot :) Commented Dec 21, 2017 at 13:15
• One more thing, it can be a PIPO register? Commented Dec 21, 2017 at 13:46