NAND technology - ecc error

Nand technology has some issues, which I find it a bit difficult to understand. It is said in nand devices that manufacture guaranty that a page will have no more than X (4/8/16,etc according to nand device) failed bit.

1. Is it that the manufacture can really guarantee that there shall never be more than this amount of failed bits is a single page ?
2. Is it that the failed ecc happens just randomly, after some time ?
3. Is it that re-program the failed ecc page, shall recover its flip bits to the correct value ?

Thank you, Ran

1. No, it's all a game of probabilities. You just define a probability (e.g. $1-10^{-14}$) that all pages fulfill that criterion, the manufacturer models the stochastic process that leads to errors and makes observations of that process, and you so get to a probability that indeed your criterion is fulfilled.