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I was reading wikipedia page on Signal Integrity and got stuck with this paragraph. It says:

The channel flight time (delay) of the interconnect is roughly 1 ns per 15 cm (6 in) of FR-4 stripline (the propagation velocity depends on the dielectric and the geometry). Reflections of previous pulses at impedance mismatches die down after a few bounces up and down the line (i.e. on the order of the flight time). At low bit rates, the echoes die down on their own, and by midpulse, they are not a concern. Impedance matching is neither necessary nor desirable. There are many circuit board types other than FR-4, but usually they are more costly to manufacture.

As far I know, Digital signal bandwidth is function of it's rise and fall time. Hence, Reflected power will dependent upon rise and fall time of the signal, not on bit rate of the signal. However, in the above paragraph, it is mentioned that for low bit rate signal reflected power won't effect the original signal. I am not able to understand the above statement. Can someone help me?

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The magnitude of the reflection can't be more than 100%. And no line is loss free. After some time, the ring caused by the reflection will die away due to losses.

If the bit period is long, the ring will (more likely) have died away before the middle of the bit period, which is the ideal time to sample the bit.

If the bit period is short, the ring may still be ongoing at the middle of the bit period, and thus cause an error in sampling the bit correctly.

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  • \$\begingroup\$ Worth noting that, for low bit rate signals, it's desirable to reduce the slew rate where possible to minimize ringing anyway. FPGAs, for example, typically have the capability to adjust slew rate on outputs. \$\endgroup\$ – kjgregory Dec 21 '17 at 21:49
  • \$\begingroup\$ Am I correct on bandwidth of Digital signals? Bit rate has any effect of spectral density and bandwidth? \$\endgroup\$ – abhiarora Dec 22 '17 at 8:07

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