I've just learned that digital CMOS inverters can be configured to perform analog functions (most notably oscillators and amplifiers). However, many of the examples tend to favor old CD4000-series devices. In addition, this application note mentions in Section 3 that the use of buffered inverters can cause stability issues.

  1. Which logic families can be reliably configured to perform linear operations? Which families should be avoided?
  2. Will "special" protection circuitry such as the 5V-tolerant I/O for AHC and LVC cause additional stability issues or prevent linear operation?
  3. What would happen if I tried to build a linear circuit using a TTL-compatible device (HCT, ACT, AHCT)?
  4. Is it considered bad practice to use digital ICs in their linear region?
  • 1
    \$\begingroup\$ Wow what a good question.Maybe the old school CMOS devices gave better bias stability because they had much more internal resistance .Maybe the old school devices were less likely to go unstable because they were by modern standards very slow .I can see that unbuffered would be better .I am looking foward to seeing some answers to this question. \$\endgroup\$
    – Autistic
    Dec 23, 2017 at 7:37
  • \$\begingroup\$ Look at the functional diagrams for the inverters in the 1st logic series - eg 4000 CMOS. They are effectively a single MOS transistor pair. The buffered gates have two (or more) stages - an inverter and then non inverting buffer.The basic transistor pair better matches the desired inverter. \$\endgroup\$
    – Russell McMahon
    Dec 23, 2017 at 13:30

5 Answers 5


All logic families like to use buffered inverters, because those are more reliable and use less power in digital applications. However, unbuffered inverters are useful to build crystal oscillators, so they exist in many families; search for 74xx1GU04.

A 5 V-tolerant I/O has no ESD protection diode to VCC, so it tends to have less capacitance, and distorts the signal less if it exceeds VCC.

TTL-compatible inputs have a lower switching threshold, so they are no longer symmetric between VCC and ground.

Unbuffered gates are meant to be used in linear circuits; buffered gates are unlikely to work at all.

Another useful application note: Understanding (un)buffered CD4xxx characteristics.

  • \$\begingroup\$ Those who understand that all logic is Analog; no explanation necessary, those who can easily learn, already know; Bode Plots, phase margin of 1 vs 3 stage, Vol/Iol for each logic family vs Vcc. Otherwise no simple explanation possible. CD4xxx worked well 3~18V, All others should work similar by scaling Vcc/RdsOn for Iq \$\endgroup\$ Dec 23, 2017 at 20:46
  • \$\begingroup\$ I've used many Buffered gates for high gain amplifiers from DC to RF but it does require analog design skills. ( when in a pinch, not as a rule) \$\endgroup\$ Dec 23, 2017 at 21:54

You have to remember logic gates like invertors are really just simple analog circuits, comparators, tailored to work well with an analog input signal that basically has two stable states, high and low.

As such, just like you can use op-amps as logic devices, simple logic devices can also be used in an analog role.

Invertors in particular fill this role nicely, since what you really have is a simple comparator/op-amp with the negative pin exposed as the input and the positive pin basically "connected" to half rail. (Or some other point for TTL etc.) Because they expose the negative pin, you can use negative feedback loops in the same way you do with op-amps. Non inverting logic is less useful.

How well they work in an analog role is of course dependent on the nature of the particular gate. Older devices are very simple matched transistors, the buffered variety have more internals that make them less linear.

Logic devices do however have a tendency to open-circuit, or worse, shoot-though, when the signal is between logic levels so using them as simple amplifiers for low frequency signals is not a great idea.

However using them as part of a delay circuit, or as the driver in an oscillator, they work well especially if the gate is a Schmitt Trigger with it's built in hysteresis.


I belatedly wanted to add a few points that weren't elaborated by others.

While it is customary to use unbuffered gates as linear amplifiers, there are a few drawbacks that must be borne in mind.

Perhaps most importantly, the parameters are poorly specified. While an amplifier datasheet has a lot of information about the amplifier properties, you will usually find very little such information in the datasheet of a logic device. Furthermore, there are bound to be large tolerances and variability over operating conditions (operating voltage, temperature, ...). Hence, you may only want to employ those devices in circuits that can tolerate such large variations.

Unbuffered inverters are available in various different CMOS logic families, starting with the old 4000 series on the slow end, up to the quite fast LVC range. Their properties differ markedly. You want to have a close look at power consumption in particular, since power draw tends to be at maximum when the input voltage is mid-range between high and low, where both transistors conduct simultaneously. This is going to be very dependent on operating voltage, too. It gets worse the faster and higher output drive the logic family is. This is why the 4000 series is fairly benign, whereas LVC type logic is much harder to deal with.

Depending on the logic family, there may also be a specified maximum signal rise/fall time, which indicates that the input level isn't supposed to stay between high and low for long. If you violate this, you don't just get high power consumption, you may also run into stability problems. It might even affect the reliability of the circuit, due to the heat generated in a fairly small pair of transistors. TI application note SCBA004 has more to say about this.

Bottomline is: You may use those devices for linear applications if you are aware of the serious limitations. Their low price may be attractive, but the drawbacks that come with the simple circuit are substantial.


Digital ICs operated in their 'linear' region may not be so linear. Some decades back I designed a product using a CD4xxx inverter chip in a ring oscillator. The manufacturer substituted a "modern" digital part (IIRC HCT), which suffered shoot-through when operated in it's 'linear' range (pull-up and pull-down output transistors turned on at the same time). Needless to say, the chip got smoking hot ;-)

So, to answer your question, it is generally bad form to use digital ICs as linear devices except in very rare circumstance!


My goto CMOS solution

enter image description here

  • All Logic I/O's have Analog characteristics in the linear region between Vdd & Vss.

  • Any Logic family can be used, given the understanding that negative feedback linear amplifiers must have good phase margin at unity gain and sensitivity to Vdd and suppliers.

- Added

  • the 74HCT or any 74xxT is TTL input threshold compatible at 1.5V instead of Vdd/2 which is the same thing when you get to Vdd=3V. With self-biasing with negative R feedback the output duty cycle will shift trying to reach 1.5Vdc at the input so depending on the signal level that may trigger the ESD clamp diodes to ground

  • Not everybody will be successful 1st time, just as in Linear and RF design without full awareness of impedance of the circuit, supply and layout, the cheap and dirty CMOS buffered inverter has amazing gain bandwidth product of >150MHz with >60dB gain for pennies per inverter.

Self-biasing is trivial when the input is AC coupled, but choice of a buffered inverter increases the technical challenge. The sensitivity to oscillation increases, when the closed loop gain is much lower than open loop gain as it is not internally compensated like Op Amps (OA).

  • Buffered inverters are treated more like high gain video amplifiers than an OA.

The open loop gain for a 1-stage inverter or unbuffered (UB) is 20dB minimum and >60dB for buffered (B) 3 stages. When using Zf/Zs, for negative feedback one must AC couple the input and outputs just as in a single supply CMOS Op Amp. The Zf is usually selected with high resistance for low current self DC biasing of the input but too high will result in a slow turn on time for input voltage settling to Vdd/2 from R2C1.


simulate this circuit – Schematic created using CircuitLab

The buffered (B) inverters have 3 times the dB linear gain of unbuffered(UB) so as video amplifiers have interesting behaviors if you need 60dB gain with Zout from 20 to 500 Ohms driver impedance. Where Zout=RdsOn=Vol/Iol @~ x mA

Other details

Given the history of CMOS logic since 1970, there are dozens of standard family prefixes like {4xxx, 'HCxxx & 'ALCxx}. All the analog characteristics are not specified directly the datasheets, such as RdsOn, Ciss and Coss, but we know these limit current drain and large signal bandwidth. You may appreciate FET behavior such as RdsOn vs Vgs is determined by Vss range and that each generation either increased speed , lowered power consumption at speed or both. This resulted in smaller lithography, lower Vdd ranges and lower RdsOn driver values.

  • You may already know that RdsOn is fairly consistent (50%) for each 54/74 CMOS series family which is Vss dependent. Since rising Vgs naturally lowers RdsOn an. The low Vss range is limited by speed from rising RdsOn significantly and the higher range raises cross-conduction current and power dissipation.

I expect ( but have not verified) every logic family can be used as a linear amplifier. Each linear amp. must follow rules to make linear and stable. However depending on layout inductance and other impedance affecting unity gain phase margin, external compensation to a 1st order pole may be necessary as kn how Op Amps are designed.

For best results, the designer must have a good idea of all the impedances * Z(f) of the circuit vs frequency even if there is a wide tolerance of ~ +/-50% for all suppliers. Never underestimate that these may change significantly, so your Approved Vendor List,AVL must only include the ones you have verified for each part number in any design. Otherwise you must figure out how to avoid these problems by design and testing. But generally I have found the Logic specs that reflect the RdsOn (or driver ESR) limits are consistent for all vendors.

  • These * include source an estimate of Z(f) of power and driver impedance to be << Zout , layouts and decoupling caps at the operating bandwidth for the supply across each chip. and the CMOS Zout =RdsOn out . The reason unbuffered inverters were more stable and recommended is because the single stage gain is normally adequate for crystal oscillators (XO) when self-DC biased with 1~10M feedback R.

I assume you have some idea of Control Theory or Bode plots. Since each CMOS stage is an inverter, Buffered inverters have 3 stages of gain G(s) and more phase shift vs \$f_{BW}\$~\$ 0.35t_R\$ and thus less stability with more feedback H(s).

Those who can easily learn, already know; Bode Plots, phase margin of 1 vs 3 stage amps, Vol/Iol for each logic family vs Vcc. Otherwise no simple explanation possible. CD4xxx worked well 3~18V, All others should work similar by scaling Vcc/RdsOn. For low impedance loads (~50), the Pd in the driver can be greatly reduced by AC coupling. 74ALCxx has about 25 Ohms @3.3V, 74HCxx has about 50 Ohms +/-50% @5V over temp.

  • \$\begingroup\$ Such a lack of appreciation for Analog Wisdom tisk tisk \$\endgroup\$ Dec 24, 2017 at 14:33
  • \$\begingroup\$ About the AC coupling.. This is a little bit off-topic but still. I'm trying to make a quadrature FM detector with a XOR gate as phase detector. The input signal is a 3.3V square wave from CMOS oscillator. The problem is that the phase-shifting RLC circuit removes DC level from the input signal. So can I just plug an AC-coupled signal into the XOR gate or not? \$\endgroup\$
    – Archimedes
    May 26, 2018 at 16:36
  • 1
    \$\begingroup\$ No. The DC self bias would track towards Null phase detection or 50% avg. or Vdd/2. The proper way is quadrature f/2 and use LPF to control VCO using DC biased reverse diode AC coupled in resonator for a “DIY” PLL vs IC Detector. But depending on excess BW does well as an FM Limiter. If not then, use ICL or ECL limiter. \$\endgroup\$ May 26, 2018 at 17:06
  • \$\begingroup\$ looks like -3 people with negative attitudes \$\endgroup\$ Apr 11, 2019 at 0:12

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