# frequency and type of pulse for time domain reflectometer (TDR) [closed]

I would like to apply the time domain reflectometry method in an fpga. However, I could not find information about the frequency and type of pulse used by reflectometer.

Can anyone give me a guide?

## closed as too broad by PeterJ, Harry Svensson, Chupacabras, Sparky256, Voltage SpikeDec 27 '17 at 5:29

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• I think the better question not which frequency, but rather what rise time (how fast is the rising edge) and how long is the pulse. Both will depend (I think) to some extent on the frequencies of interest (what signal your cable will carry in normal operation) and the length of the cable. But, I've never worked with that type of thing so I'm going to watch this question and see what the knowledgeable folks have to say. – JRE Dec 23 '17 at 11:48
• I think it will also depend on the length of what your measuring, the max pulse length can not exceed the phase speed (material corrected) / cable length. – MadHatter Dec 23 '17 at 16:24
• The time resolution will be determined by the delay in the line and then the delay in the gates, but you don't have to do any of this, because there are IC's available that have this problem solved for you, better than any FPGA can solve it. – Voltage Spike Dec 27 '17 at 5:29

However, I could not find information about the frequency and type of pulse used by reflectometer.

Typical TDR instruments use a square pulse and measure the response only to one edge, so they are measuring the response to an approximation to the unit step function $u(t)$.

The frequency range they're able to measure depends on the rise time of the stimulus pulse. Since the Fourier transform of even an ideal $u(t)$ has $1/f$ characteristic, and the feedlines to the device under test (DUT) typically have low-pass characteristics as well, it is quite challenging to measure very high frequencies with TDR, although commercial instruments from Tektronix or Keysight can reach the neighborhood of 20 GHz at least.

Another challenging in implementing TDR with an FPGA will be sampling the response with low noise and low jitter.

• Based on your comment, does it mean that I can only apply low frequency pulse on fpga? If it does, is there a formula to calculate the desired frequency? Besides, the challenge you mentioned (low noise and low jitter), does it mean that I cannot check the changes easily? – Erile Dec 24 '17 at 3:11
• FPGAs nowadays can produce some pretty fast edges. You'd have to read the datasheet for your device to know how fast. – The Photon Dec 24 '17 at 3:14
• Ok, I will check it. It is something related to the pll, right? Then, is there any formula can calculate the frequency I'm going to use? Or I can refer to previous comment of @MadHatter? – Erile Dec 24 '17 at 3:53
• It's nothing to do with the PLL. The key spec is the rise time of the digital outputs, in whichever IO configuration you plan to use. – The Photon Dec 24 '17 at 3:56
• Sorry, but I didn't get your words. Can you please explain more about it please? – Erile Dec 24 '17 at 9:01