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So I have been reading about OpAmps and also simulated a bit with Ltspice. I made a simple Integrator with an LM324 OpAmp and its getting close to the positive rail but Its not really exact.

What is causing OpAmps not reaching exact positive rail values ? Is it the circuit inside the OpAmp limiting it ?

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  • \$\begingroup\$ No schematic ?? \$\endgroup\$ – Mitu Raj Dec 23 '17 at 20:10
  • \$\begingroup\$ There are opamps based on CMOS technology which have a "rail-to-rail" output (and usually inputs as well) which do almost reach the supply rails. If you're not loading the output too much that is. \$\endgroup\$ – Bimpelrekkie Dec 23 '17 at 21:30
  • \$\begingroup\$ CMOS opamps, with heavily forward-driven gates, can have Rout << 1 ohm. A 1Kohm Rload allows your Vout to be only 0.1% away from rails. For example, in 0.6u process, the Rout of FETs is 1/( K * W/L * Ve); with 100uA/volt^2 * 1,000/1 * 5 volts, the Rout is 1/0.5 amp/volt or 2 ohms. Assuming your Nch FET is 1,000/1 or 10 stripes of 100/1. \$\endgroup\$ – analogsystemsrf Dec 24 '17 at 1:51
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enter image description here

Figure 1. The LM324 op-amp internal circuit.

Note that when the output is driven high that the Darlington transistor pair, Q5 and Q6 must turn on. Since the base-emitter junctions of Q5 and Q6 each drop about 0.7 V when on it stands to reason that the most we could expect out of this circuit is V+ - 1.4 V. Since Q5's base current comes from the 100 µA current source we must allow for the voltage drop of that too.

When swinging negative Q13 provides a path to ground. Since its base must be pulled low by Q12 to turn on we have a similar, although slightly improved, version of the problem.

You should be able to simulate each of the cases for the top and bottom drive circuits and see what the minimum and maximum output voltages are in each case. Then compare these with the datasheet.

Note that the voltage range will degrade as the load Iout increases (mA) .

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  • \$\begingroup\$ But it's also worth noting that if you replaced the output stage with a single PNP stage (no Darlington), you could do much better. The fact that this isn't generally done says a lot about the limitations of transistors. \$\endgroup\$ – WhatRoughBeast Dec 23 '17 at 20:24
  • \$\begingroup\$ That is why some op-amp designs have a pull-up resistor on the output tied to Vcc. This gives a better 'off' voltage for p-channel mosfets or pnp transistors. \$\endgroup\$ – Sparky256 Dec 23 '17 at 20:31
  • \$\begingroup\$ No problem. The range of max swing {Vpp/Io} is quite nonlinear due to DC emitter current sink and has lowest ESR above Vo>2Vdc ( above Vee.) Which also causes the Vo(sat) which is much more than a simple common emitter(CE) Vce(sat). Since CE's are current pumps that turn to switches when saturated, for low ESR output they use at least 2 stage Common Collectors. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Dec 23 '17 at 22:58

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