How do you address 2 x 512 kB RAM and 2 x 1024 MB RAM with 40 address lines? Memory is byte addressable, problem is to find out enough address lines to address all 4RAM and designing appropriate partial decoder to select each RAM?

For eg; one 513 KB can be addressed with 19 and 1024 with 30 address lines, Address space on each RAM:

Address lines:  A30   A29    A28 ... A20   A19   A18   A17.......A0
    1st 512KB:                        0     0     0     0.........0
                                      0     0     1     1.........1

    2nd 512KB                         0     1     0     0.........0
                                      0     1     1     1.........1

    1st 1024MB                        1     0     0     0.........0
                1      0      0 ..... 0     1     1     1.........1

    2nd 1024    1      0      0.......1     0     0     0.........0
                1      1      1.......0     1     1     1.........1

Which address lines are enough for memory select chip lines and what decoder i use for selecting RAM?

  • 1
    \$\begingroup\$ You're making enough mistakes when writing the questions that I can no longer trust that you have anything right. VTC unclear. \$\endgroup\$ – pipe Dec 24 '17 at 0:49
  • \$\begingroup\$ Whether you call the lowest address bit a byte-select or array-select or just A0 is semantics. You have 4g possible byte locations, and that takes 32 bits. Does your system have 36 or 40 address lines? \$\endgroup\$ – AnalogKid Dec 24 '17 at 0:55
  • \$\begingroup\$ question edited to make it more clear \$\endgroup\$ – Ajakma Dec 24 '17 at 1:02
  • \$\begingroup\$ Embedding the byte-select address bit (A18) in the middle of the address field is non-standard and can lead to problems. Since a byte is smaller than a word, better to make A0 the byte select and start the word address with A1. In this way the least significant address bit is truly the least significant. \$\endgroup\$ – AnalogKid Dec 24 '17 at 1:05
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    \$\begingroup\$ Putting the 512 array first in the address space orphans 3.999 billion addresses. Better to put the larger array first. \$\endgroup\$ – AnalogKid Dec 24 '17 at 1:07

1) You have the answers right in front of you..lol! A0-A18 are good for 512 KB, so use A19 to enable the second 512KB. That is 1 MB so far. Use A0-A19 with A20 to enable the next 1 MB IC. Use A0-A20 with A21 used to enable the last 1 MB.

2) If you wire A18, A19 and A20 to a 74AC138 address select(74LVC138 if 3.3 volt memory), it will give you 8 blocks of 512 KB that are active low Y0-Y7. You MUST control the chip select pins (CS) so that the outputs go low after the address lines are stable. Only one 'Y' pin at a time can go low.

3) Make sure you wire up all needed address lines, stoping at A20. Use Y0 and Y1 for the first two 512 KB chips. Use Y4 && Y5 to enable the first 1 MB chip, and Y6 && Y7 to enable your last 1 MB. The && I typed means use a fast 74AC08 AND gate or 74LVC08 if 3.3 volt logic to sum together 2 'Y' address lines, with a single active low output for your 1 MB IC's.

4) Don't forget to wire up your active low read (RD) and write (WR) lines. They should be the last lines to be active, though some designs may use chip select (CS) as a final strobe after all other lines are settled to a study state.

5) Why you thought you needed 30 to 40 address lines I do not know (That would be for GB of memory). If the lower addresses are already in use shift the Y0 and Y1 lines to Y2 and Y3, which gives you 1MB of spare room at the bottom of your memory map.

NOTE: If you are trying to add this to an existing memory map with lots of I/O already in use then I would re-think this. Once you understand memory mapping you will know what you can and cannot do.


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