# Design logic circuit to address 2 x 512 kB RAM and 2x1024 MB RAM with 36 address lines? [closed]

How do you address 2 x 512 kB RAM and 2 x 1024 MB RAM with 40 address lines? Memory is byte addressable, problem is to find out enough address lines to address all 4RAM and designing appropriate partial decoder to select each RAM?

For eg; one 513 KB can be addressed with 19 and 1024 with 30 address lines, Address space on each RAM:

Address lines:  A30   A29    A28 ... A20   A19   A18   A17.......A0
1st 512KB:                        0     0     0     0.........0
0     0     1     1.........1

2nd 512KB                         0     1     0     0.........0
0     1     1     1.........1

1st 1024MB                        1     0     0     0.........0
1      0      0 ..... 0     1     1     1.........1

2nd 1024    1      0      0.......1     0     0     0.........0
1      1      1.......0     1     1     1.........1


Which address lines are enough for memory select chip lines and what decoder i use for selecting RAM?

• You're making enough mistakes when writing the questions that I can no longer trust that you have anything right. VTC unclear. – pipe Dec 24 '17 at 0:49
• Whether you call the lowest address bit a byte-select or array-select or just A0 is semantics. You have 4g possible byte locations, and that takes 32 bits. Does your system have 36 or 40 address lines? – AnalogKid Dec 24 '17 at 0:55
• question edited to make it more clear – Ajakma Dec 24 '17 at 1:02
• Embedding the byte-select address bit (A18) in the middle of the address field is non-standard and can lead to problems. Since a byte is smaller than a word, better to make A0 the byte select and start the word address with A1. In this way the least significant address bit is truly the least significant. – AnalogKid Dec 24 '17 at 1:05
• Putting the 512 array first in the address space orphans 3.999 billion addresses. Better to put the larger array first. – AnalogKid Dec 24 '17 at 1:07