# <Verilog> Mixed blocking & non-blocking assignment

I would like to ask three questions about blocking & non-blocking assignment.

The first question is that How the blocking and non-blocking statement works when they are combined.

following the book "FPGA_Prototyping_By_Verilog_Examples" it says that

When an always block is activated, the right-hand-side expressions of nonblocking assignments are evaluated at the beginning of the time step.

Based on the above statement about a non-blocking statement, I've expected that the below always block would require two clocks for assigning value of a&b to the q0, but the book says it can do it in one clock cycle.

always @(posedge clk)
begin
abO  =  a & b ;
qO  <=  abO;
end


At the first glance, I've thought that the value of ab0 (RHS of non-blocking assignment) will be stored in somewhere before the always block is executed and to be used in the q0 <= ab0;. Therefore, I assumed that the value of ab0 will be estimated at the first clock cycle and the estimated value of ab0 will be assigned to the q0 in the second rising edge of the clock.

So my question is, when the value of RHS of non-blocking statements are decided when they are used with the blocking statements. If it is determined regardless of the blocking statement please let me know.

The second questions is How the non-blocking and blocking statements affects the real hardware?

I've read many articles that say the nonblocking and blocking assignments do not have any effect on the synthesis, but only regards to the simulation. If it is just about the simulation, How the hardware really works to executed instructions inside always block? Does it sequentially execute the instructions one by one like the C code?

As far as I know the ground rule is

• use the non-blocking assignment in the sequential circuit.
• use the blocking assignment in the cobinational circuit.

However, it seems that using the non-blocking assignment in the combinational circuit and blocking assignment in the sequential circuit are all legitimate and allowed or even mixed!!!

So, my last question is What is the advantage of mixing two assignments or what kind of cases are there to use non-blocking assignment in the combinational circuit and blocking assignment in sequential circuit?

Articles that say "nonblocking and blocking assignments do not have any effect on the synthesis, but only regards to the simulation" are incorrect. It is true there are certain cases where choosing either assignment operator has no affect on the synthesized hardware, but there are cases where it does make a difference.

One needs to realize that code you write executes in serial order within a begin/end block regardless of whether it represents a sequential or combinational circuit. Both simulation and synthesis tools need to implement the behavior you specify.

You can model both sequential and combinatorial circuits with just blocking assignments (in fact, non-blocking assignments were a later addition to the Verilog language). You can determine if the code represents a particular kind of circuit by looking at the order of assignments to the LHS variables with respect when the same variables are used in the RHS.

always @(posedge clk)begin
ab  =  a & b & q0;
q0  =  ab;
end


Because ab appears in a blocking assignment statement before appearing on the RHS, it is considered combinational (write before read). And the value of ab gets updated immediately before executing the next statement. And since q0 appears on the RHS before appearing on the LHS, it is considered sequential (read before write).

But if we add another always block that uses ab on the RHS, that usage is considered sequential.

always @(posedge clk) begin
c = ab;
end


Now ab represents sequential logic in that block because the other block executed on a clock edge, sampling the values of a and b. But now we have a simulation race condition because although the execution order within a begin/end block is serial, there is no defined ordering between different always blocks triggered by the same clock edge - you don't know if the second always block has the updated value of ab from the first always block.

The non-blocking assignment solves this race simulation race condition by delaying the LHS assignment until after everything else that was supposed to execute at the same time step. If we change the assignment to ab in the first always block to:

always @(posedge clk)begin
ab  <=  a & b & q0; // NBA
q0  =  ab;
end


Now the second always block is guaranteed to have the "old" value of ab. But this also does affect the statement that follows it in the same block. It now assigned the "old" value of ab to q0. So now it does take two clock cycles to get the value through to q0.

• Very good answer! I really appreciate it. By the way, I have a further question. You mentioned that a variable is sequential when it is read before write and combinational when it is written before read respectively. As far as I know, we would call the circuit is sequential when it requires memory and is combinational when it doesn't necessitate the memory. Then If more than one sequential and combinational variables are mixed in the always block, is it a sequential circuit? or combinational circuit? Dec 26, 2017 at 12:02
• Out of curiosity, how the verilog schedules multiple always block? I've assumed that the all always blocks are to be executed concurrently, but it seems that there exists slight timing difference in each always block, even they are synchronized with the same clock. Furthermore, if there exists time gap and if it is too long to finish one always blocks before executing another, a race condition would occur even though we use the non-blocking assignment. Thanks a lot once again. Dec 26, 2017 at 12:32
• And the last question is about what made the non-blocking assignment to be introduced. You've mentioned that the non-blocking assignment was introduced after the blocking assignment was used in first. Is it because of the race-condition? Dec 26, 2017 at 12:38
• An always block can describe a mix of sequential and combinatorial logic. Analysis is done on each variable You need to study the simulation semantics section of the LRM to see how it schedules always blocks. Dec 27, 2017 at 7:27
• Hi, thanks for a recommendation. Is it a right article you've mentioned?staff.ustc.edu.cn/~songch/download/IEEE.1364-2005.pdf Dec 28, 2017 at 8:00