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I do not know how to compensate the DC-offset caused by the Input bias current.

schematic

simulate this circuit – Schematic created using CircuitLab

How to compensate the input current bias DC offset? I know the "trivial" method by adding the additional voltage (regulated by the potentiometer) to the OP-AMP input. But when I switch the SW1 the offset will change and it will require the additional calibration. Is there any "automatic" method to archive it?

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  • \$\begingroup\$ Huh? What? Try asking a coherent question, and rewrite in English while you're at it. \$\endgroup\$ – Olin Lathrop Dec 26 '17 at 17:51
  • \$\begingroup\$ This opamp has 1.4-6uA input current. I need to compensate it somehow when the input circuit is like this shown on the picture. \$\endgroup\$ – P__J__ Dec 26 '17 at 17:54
  • \$\begingroup\$ @OlinLathrop could you explain what you mean? \$\endgroup\$ – P__J__ Dec 26 '17 at 17:56
  • \$\begingroup\$ @PeterJ_01: You have a problem but you didn't explain it. You have omitted the component values for R6 and R8, no explanation for the signal input and no explanation about what SW1, R3, 4 and 5 are for. C1, R7 and C2 are probably irrelevant to your question. \$\endgroup\$ – Transistor Dec 26 '17 at 18:03
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    \$\begingroup\$ Can you use an op-amp with a lower bias current? \$\endgroup\$ – Robert Endl Dec 26 '17 at 22:17
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Add series resistors to the input divider so the resistance looks the same looking into each switch position, then match that to R6||R8 (increasing the latter if necessary).

For example, in the top switch position (assuming DC coupling) add a resistor Rx1 such that Rx1+ R1||(R3+R4+R5) = R6||R8. And so on for the other two positions.

schematic

simulate this circuit – Schematic created using CircuitLab

Although this answers your question, it's probably not what you want to do unless this is a pointless homework exercise. I say this because normally amplifiers with relatively high bias current are used for either high speed or low noise and your high impedances mean that will likely not work out well- because of input current noise for low noise or parasitics in the case of high speed.

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  • \$\begingroup\$ I will try it now. I have the circuit on my bench \$\endgroup\$ – P__J__ Dec 26 '17 at 18:11
  • \$\begingroup\$ Keep in mind this compensates only for the output offset due to the input bias current, not that due to the input offset current. \$\endgroup\$ – Spehro Pefhany Dec 26 '17 at 18:12
  • \$\begingroup\$ Thank you - I know. But the input bias current offset in this case is about 1.8V \$\endgroup\$ – P__J__ Dec 26 '17 at 18:14
  • \$\begingroup\$ And you can't reduce the divider resistors by 10:1 or whatever, I suppose. \$\endgroup\$ – Spehro Pefhany Dec 26 '17 at 18:16
  • \$\begingroup\$ Unfortunately I cant reduce them \$\endgroup\$ – P__J__ Dec 26 '17 at 18:16
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Having just read thru the EXAR CLC2007 high speed opamp datasheet, with its promised 0.5pF Cin, plus resistor Cparasitic + PCB parasitic + switch/analog mux parasitic, I'd expect 5 to 15 pF capacitance on the Vin+ of the opamp.

That Capacitance, 10pF, along with 100Kohm resistance (if not even higher), gives a TAU of 1,000 nanoseconds. Thus the OpAmp's promised high-speed is not put to use.

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