1
\$\begingroup\$

I'm new FPGAs, and working through the "IntroToSpartanFPGABook" PDF.

I'm looking at the "constraints.ucf" file, and (because I'm lazy), it occurred to me that I could create one "constraints.ucf" file for my (Papilio) Megawin, which I can then use for all projects, without modification. Switch 1 will always be on the same wire.

This works ok, except that everything that I DON'T use generates a warning:

WARNING:PhysDesignRules:367 - The signal <switch_1_IBUF> is incomplete. The signal does not drive any load pins in the design.

I understand that it is 100% correct, I am not using that switch (or LED), but if I remove the declaration, I need to have a different constraint file for each project (commenting and uncommenting as I go).

Is there a way of saying the following:

NET led_0 LOC = "P3" | IOSTANDARD=LVTTL DontGenerateWarningsIfNotConnected;
\$\endgroup\$
0
\$\begingroup\$

You don't use the same ucf file for all projects for the same reason you don't use the same schematic.

Once you've described what you want to achieve in the ucf file, these warnings let you know if you've had a 'fat finger' moment.

If you want to forgo this simple check, then you could write a master ucf file, and a simple VHDL parser that copies the master, auto-commenting out lines it doesn't find used in the VHDL.

A halfway house that doesn't involve as much upfront work is to manually copy your master 'all commented out' ucf file into your project folder, and manually remove comments from those lines you are going to use.

Alternatively, if you RTFM carefully, you may find a way to suppress specific warnings (it's not advisable to suppress all warnings).

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.