I need a 500MHz FIR filter for filtering ADC samples (500MSPS).

After the filtering a few samples needs to be stored in a buffer, for a simple peak detection algorithm.

I have been developing some VHDL code, and used a Xilinx FIR filter library to create the filter.

But after looking into the prices of Xilinx FPGA's that would do a 500MHz FIR filter, well above $100, my jaw hit the desk.

Is there any good and low cost ( less than $50) FPGA for doing this?

  • \$\begingroup\$ How you interface ADC to FPGA? LVDS, something else? \$\endgroup\$ – mazurnification Jun 28 '12 at 12:14
  • \$\begingroup\$ Yes, or some support CMOS, not decided yet. \$\endgroup\$ – JakobJ Jun 28 '12 at 12:15
  • \$\begingroup\$ How wide are your samples? \$\endgroup\$ – Martin Thompson Jul 2 '12 at 14:34

Until recently, 500 MHz would have been considered a fairly fast clock, requiring a relatively high-end (and high-cost) FPGA. But nowadays a low-cost part ought to be able to do that.

However, there are other specs that are equally important to the data rate to determine what part will work for you:

  • What's the data width? A 16-bit adder requires a longer carry chain than an 8-bit adder and so requires a longer clock period in a given architecture and speed grade.

  • How many taps in the filter? A very large number means working with RAMs instead of just registers, leading to a new set of timing requirements and new considerations for which parts will meet your needs.

  • What are the weights? Equal weights on all taps means a much simpler calculation. If you have different weights on each tap, you might need to redo the complete set of add-multiplies for each new input sample, making for a much harder problem.

But if your other specs aside from clock rate are fairly relaxed you might be able to do this in a low cost device.

  • All the FPGA vendors have low-cost FPGA lines that can be priced as low as $5 each. For example, Xilinx has Spartan and Artix, Altera has Cyclone, etc. In recent generations, these parts should be able to do at least minimal logic at 500 MHz. But if you have to do wide add-multiplies or something, you may have to do some very careful pipelining or other tricks to get them to work. Be sure to look at the most recent generation of parts to get best performance, best pricing (unless a family is absolutely brand-new), and longest assurance of supply.

  • Recent CPLD's from Altera and Lattice are really small FPGAs with built-in flash to allow automatic reconfiguration on power-up. For a simple filter, these might be sufficient.

But without knowing your complete design we can't tell you what device will work. You'll have to just try designing it for each candidate part and use the vendor's synthesis tools to find out if you can meet timing in each case.

  • \$\begingroup\$ +1 - "You'll have to just try designing it for each candidate part and use the vendor's synthesis tools". That's the real answer here is to actually see what part your design can target. Then play the limbo game with your code optimization/timing until you've gotten it to fit in the cheapest eval board you can. \$\endgroup\$ – Joel B Jun 28 '12 at 20:50
  • 1
    \$\begingroup\$ Thank you for your answer. After some recalculation I have found that 300MHz should be sufficient, which means cheap Spartan 6 FGPA's or alike will do the job. :-) \$\endgroup\$ – JakobJ Jun 29 '12 at 9:23

Note that a convolution style filter requires doing doing many multiply-accumulate operations per input sample, which means that you either need a clock rate that is many times the sample rate, or you need to use many multipliers to operate in parallel, or some combination of the two.

If you can tolerate some downsampling, one efficiency is a polyphase FIR filter, which only does the calculations necessary to produce the less frequent samples at the output rate. Another common choice is a CIC filter, which is quite efficient at high decimation ratios but has a rectangular impulse response and hence a sync-function frequency response. Frequently the two are used in combination.

Another option in some cases is to not process the data at the input rate, but to buffer it and then process it more slowly; of course this only works for intermittent evaluation which doesn't sound like what you want with peak detection.

If you only need a little lowpass filtering before the peak detect to remove some noise, you might consider an analog implemention or an IIR instead of an FIR. You could also consider implementing a PID loop which follows the input signal, and taking your output from the loop accumulator.


In order to get a sensible solution you need to step back and look at the requirements:

1) What does the typical input signal look like? Unipolar? Bipolar? Frequency? Range? Envelope? Modulation? Noise?

2) Is peak detection all that is required?

3) How quickly/regularly do you need to detect the peak?

4) How accurately do you need to measure the peak?

5) Why do you need to FIR if only peak detecting?

6) Is the FIR frequency selective or simply averaging/noise filtering?

7) If the ADC data is used elsewhere at what rate is it used?

To me filtering before peak detection implies that you don't want absolute raw peak detection but rather a more conservative peak detection that ignores any spurious spikes that are not considered to be part of the signal of interest.

If so it may be more efficient to keep track of each bit read from the ADC, noting the most significant combination of bits "P" that is set at least "X" times in your period of "N" samples and simply output this value.

The higher "X" is and the higher "N" is the more noise-free and reliable your peak value reported will be.


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