I am learning to use an FPGA (Papilio development board,which has a xilinx spartan3e, using vhdl).
I need to divide an incoming pulse by a (hard coded) number.
I can see 3 options - roughly, as pseudocode (using 10 counts as an example):
- Initialize to 0, on input rising edge increase by 1, compare to 10; if they are equal, reset to 0 and trigger output pulse
- Initialize to 10, on input rising edge decrease by 1, compare to 0; if they are equal, reset to 10 and trigger output pulse
- Initialize to 9, but make sure there is at least 1 leading "0" bit, which is my output bit. On input rising edge decrease by 1. On rising edge of the output bit, reset.
The duty cycle is unimportant.
Is one of these better than the others? Is there an even better method that I haven't thought of?
Is there a "standard" way that will give the compiler the best chance of optimizing?