I am designing a universal shift register of 4 bits in VHDL.

I am also using Xilinx software to simulate the VHDL code.

I have managed to write the code which from reviewing it a couple of times, seems without errors (I understand sometimes the code can compile successfully but in fact there would be a few problems in there which aren't so obvious).

the code:

entity USR is
Port ( clk : in  STD_LOGIC;
       rst : in  STD_LOGIC;
       sir : in  STD_LOGIC;
       sil : in  STD_LOGIC;
       d : in  STD_LOGIC_VECTOR (3 downto 0);
       q : out  STD_LOGIC_VECTOR (3 downto 0);
       s : in  STD_LOGIC_VECTOR (1 downto 0));
end USR;

architecture Behavioral of USR is
signal temp: std_logic_vector(3 downto 0);



    if rst='1' then
    temp<= "0000";
    q<= "0000";

    elsif (clk='1' and clk'event) then

        case s is
        -- PARALLEL LOAD 
        when "11" =>
        temp <= d;
        q <= temp;

        -- SHIFT LEFT       [0] [0] [0] [0]
        --                  [0] [0] [0] [sil]
        when "01" =>
        temp <= d;
        temp(3 downto 1) <= temp(2 downto 0);
        temp(0) <= sil;
        q <= temp;

        -- SHIFT RIGHT      [0] [0] [0] [0]
        --                [sir] [0] [0] [0]
        when "10" => 
        temp <= d;
        temp(2 downto 0) <= temp(3 downto 1);
        temp(3) <= sir;
        q <= temp;

        -- HOLD
        when "00" =>
        temp <= temp;
        q <= temp;

        when others => null;

        end case;
    end if;
end process;    

end Behavioral;

I tried running this on Xilinx ISE simulator but when I simulate the waveform, there seems to be no changes to the outputs.


As the image above shows, when s = "11", the outputs q should be the same as the inputs d as

when "11" =>
temp <= d;
q <= temp;

Therefore the signal temp is assigned with input d and then the output q is assigned the signal temp.

Theoretically something like this should show the outputs q to be the same as input d

I cannot find a fix for this or infact all the modes (s= 00, 01, 10, 11) show no changes in the output.

Is there something that I missed?

  • \$\begingroup\$ How much debugging have you tried? Can you set q = "1111" in the reset section, to make sure what you're looking at is connected? It is basic stuff, but what you have looks good, so you can't trust anything \$\endgroup\$
    – pscheidler
    Dec 28, 2017 at 20:55
  • \$\begingroup\$ Sorry: you are right, the q<= temp change is needed but not fundamental. I am trying your circuit now but I am changing the process(rst,clk,s,d,sir,sil) to process (rst,clk). \$\endgroup\$
    – Oldfart
    Dec 28, 2017 at 20:55
  • \$\begingroup\$ I changed q = "1111" which when simulated with, showed no changes in outputs, so I assumed there was a problem somewhere in the code. \$\endgroup\$
    – Kuroro
    Dec 28, 2017 at 21:03
  • \$\begingroup\$ I've also now tried to only work with one operating mode (s = 11) and changed others to null, yet still the same problem. \$\endgroup\$
    – Kuroro
    Dec 28, 2017 at 21:09
  • \$\begingroup\$ One thing you are missing on the specific "parallel load" case (s = "11") is the semantics of signal assignment : you meant to write " the signal temp is assigned with input d and then the output q is assigned the previous value of the signal temp." \$\endgroup\$
    – user16324
    Dec 28, 2017 at 21:23

2 Answers 2


Just tried your code UNCHANGED and for me it works. enter image description here

Using Xilinx Vivado 2017.2.

  • \$\begingroup\$ That is amazing! I appreciate the help, now I know the very least that the code I've written is solid and works, I suppose the Xilinx package I am using (the 10.1 webpack - Free version for students) might be the reason for it now working. Is Xilinx Vivado 2017.2 free to use? \$\endgroup\$
    – Kuroro
    Dec 28, 2017 at 21:28
  • \$\begingroup\$ Yes, it is free. Don't forget to make the other change I recommended. And it is good practice to up the score if an answer is usefull. \$\endgroup\$
    – Oldfart
    Dec 28, 2017 at 21:34
  • \$\begingroup\$ Yes, I am currently downloading the WebPack version of the Xilinx Vivado 2014.4 since it wouldn't let me download the 2017.2 version. I have already made the changes to the code that you previously mentioned. I very much appreciate the help so far, if anything else comes up, I will be sure to ask. Thanks. \$\endgroup\$
    – Kuroro
    Dec 28, 2017 at 21:54
  • \$\begingroup\$ Xilinx ISE 10.x is very very old. Even the latest available ISE version 14.7 is 4.5 years old. \$\endgroup\$
    – Paebbels
    Jan 2, 2018 at 6:44

I checked this in modelsim 6.5, 10.4 and iSim 14.7. It gave the expected waveforms as per your code. So it seems like it is a simulator issue here or mistake in the way you simulated this design. Your simulator is never entering into your clock block. Check rising_edge(clk) instead of clk=1 clk'event. There are known issues between these two constructs in some simulators. Also try using other simulators.

However I have some suggestions in your code.

1) Process needs only clk and rst in the sensitive list, as the rest are synchronous signals as per your code.


temp <= d;

q <= temp;

"Theoretically something like this should show the outputs q to be the same as input d"

If your intention is that, Then NO. This is not c/c++. In VHDL, this is called signal scheduling. When you write this piece of code, it will infer two flip-flops connected back to back. One for temp and other for Q. If temp is updated in one clock edge with the value of D. THIS VALUE of temp is captured ONLY in the next edge by the flip-flop for Q. I.e., the temp's value is assigned to Q only in the next clock edge.


temp <= temp

This is unnecessary and has no meaning. You can leave out. Cz temp's value is retained already by the flip-flop.

  • 1
    \$\begingroup\$ Thank you very much guys, I have managed to make it work now! Much appreciated for all the advice. \$\endgroup\$
    – Kuroro
    Dec 29, 2017 at 21:56

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