I saw in many VHDL codes that data/control outputs are first assigned to signals and then to output ports, and not instantly to the output ports.
I'll give an example:
entity ex is port (clk, rst : in std_logic; .... data_out : out std_logic); end entity; Architecture ex of ex is signal data_out_sig : std_logic; Begin process(clk,rst) begin .... data_out_sig <= some_data; .... end process; data_out <= data_out_sig; End Architecture;
My question is, why do we not assign some_data instantly to the data_out port? Why does it "have to go through" the signal data_out_sig? Does this have anything to do with synthesis? Is it common practice?