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How can I create a digital counter that counts from 000 to 111 and automatically starts reverse counting from 111 to 000. I have tried with simulation it works fine, but with actual ICs I am not getting a proper output.

The following is the hand-made version of the circuit diagram that I simulated on cedar:

enter image description here

original fuzzy image

The top ones are 7 D flip-flops and the bottom ones are three JK flip-flops implementing the up-down counter.

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  • \$\begingroup\$ Post code you used with simulation. \$\endgroup\$ – Anonymous Dec 30 '17 at 8:52
  • \$\begingroup\$ Actually I have done the simulation using a softwar3 called cedar . I have the .circ file if you say \$\endgroup\$ – Ajinkya Ambatwar Dec 30 '17 at 8:53
  • \$\begingroup\$ Where I have used 7 dff in series to create a delay of 7 clock cycles. The dff are initially hence for the first 7 cycles the output from the seventh dff is 0. The negation of the 7th dff output is sent back to inpit for 1st dff hence for next 7 clock cycles I will get 1 as output. These outputs from 7th dff are sent to a up-down binary counter hence for the first 7 clock cycles the circuit counts up and for other 7 clock cycles it counts down \$\endgroup\$ – Ajinkya Ambatwar Dec 30 '17 at 8:56
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    \$\begingroup\$ Then post resulting circuit diagram. \$\endgroup\$ – Anonymous Dec 30 '17 at 9:10
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    \$\begingroup\$ IMO a better approach would be to create a 4 bit counter, where the 4'th bit controls whether the other bits count up or down. \$\endgroup\$ – Wouter van Ooijen Dec 30 '17 at 10:28
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You could do something like this:

forward and reverse bin counter

View the simulation in falstad.com

To build it1, I started with a simple 3-bit "up" counter, similar to the one below - except I used T-flip flops for simplicity, and we only need the first three stages.

up counter from allaboutcircuits.com

image credit: www.allaboutcircuits.com

And a "down" counter:

down counter from allaboutcircuits.com

image credit: www.allaboutcircuits.com

The goal is to have the circuit change from an "up" counter to a "down" counter, and vice versa, when the outputs become binary 111 and 000, respectively.

To do this, I added A1, to detect when the outputs are all high, and A2 to detect when they are all low. The outputs of these two detectors are then sent to Q4 to set and reset the direction flow. So, Q4 can be thought of as a direction controller.

Notice that when Q4 is reset (i.e. has a 0 output) the XOR gates X1 and X2 are simply voltage followers of Q1 and Q2. So, X1 and X2 essentially become transparent.

When Q4 is set (has a 1 output), X1 and X2 invert the outputs of Q1 and Q2, and therefore mimic the \$\bar Q\$ signals. And it is the \$\bar Q\$ signals which are used to create the "down" counter, in the image above.

1I'm using the "I" here because there are likely many different ways to accomplish this. Here, I'm just discussing what I did.

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(Sorry could not fit this in a comment) I can't tell you why you code is not working but the minimum logic would require only 4 FF's. Three for counting (up or down), one for the direction. The direction FF needs to be toggled:

  • on 001 if counting down
  • on 100 if counting up.

(You need two "comparators" each of 4 bits using the counter state and the direction signal)

The reason why your code is very sub-optimal is that if you have to make a counter which counts up and down to e.g. 255 your shift register becomes a bit big.
Pseudo code:

if (reset)
   count <= 000
   down <= 0
elsif (clock edge)
   if (down) 
      count <= count-1;
   else
      count <= count + 1;
   endif
   if (down and count==001)
      down <= 0;
   else
      if (!down and count==110)
         down <= 1
      endif
   endif
endif
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Since you have given no details of your physical implementation, and no data as to what your physical circuit is actually doing, it is impossible to accurately diagnose your problem.

However, I suggest (based on your diagram) that you are not properly initializing your circuit, especially your 7 FF chain. When you apply power to a real logic circuit there is no guarantee that all of the storage elements (flip-flops) will automatically start at a 0 state. This will have two possible effects:

1) The output of the 7 FF chain probably will not exhibit 7 zeros followed by 7 ones, etc, and your counters will change direction more often than you expect.

2) Even if it does, unless the 3 counter flip-flops also conveniently start at zero the up/down transition will not occur at 000 and 111.

Finally, you do not show your clock source. If it is a push-button switch, like so

schematic

simulate this circuit – Schematic created using CircuitLab

then you will experience contact bounce, and a simple push of the button will generate more than one transition.

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