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So i was working on JFET networks and in the calculation of The output impedance (Solution from the book) I am stuck in the solution My question is How can Vrd = V0 + Vgs ?

The solution picture enter image description here

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  • \$\begingroup\$ It looks like the condition for IDSS with Vi=0 and that hilite looks incorrect. \$\endgroup\$ Dec 30 '17 at 20:47
  • \$\begingroup\$ No it's correct Vi - Vgs = V0-Vrd \$\endgroup\$ Dec 30 '17 at 21:11
  • \$\begingroup\$ ok and it applies when Vi=0 such that \$V_{r_d}=V_o+V_{gs}\$ \$\endgroup\$ Dec 30 '17 at 21:41
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From looking at the diagram I would say that Vrd=Vo+Vgs-Vi but if you asume Vi=0 then it is true.

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  • \$\begingroup\$ can you please explain how did you calculate it . thnx \$\endgroup\$ Dec 30 '17 at 21:03

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