If the input meets the setup and hold time requirements, then the output is essentially "guanranteed" to reflect the input; if it violates the setup time, the behavior is no longer guaranteed or fully predictable, as you say.
Your professor may be "kind of probably" right in the sense that he may be expressing what the output signal is quite likely to end up being, especially if he is interpreting the setup time as being a deterministic description of the flip-flop's behavior, rather than a minimum requirement with possible variation from one set of conditions to the next. But your interpretation and instincts are really on target. Setup and hold times are generally used to express min/max values for which the behavior can be reliably predicted across process/voltage/temperature variations, and whenever the input violates them, the output cannot be reliably predicted.
If the flip-flop generally has up to 20ns of delay from the input to where the clock edge takes effect, then the output is most likely to end up being what the input was "around" (up to) 20ns before the clock edge, as your professor suggests. But the only thing that is specified for the device is that if the setup and hold times are met, then the output will follow the input.
So I guess in other words you may both be right to a degree, but your interpretation is 100% right, while your professor's answer is only "probably" right, and the degree to which his answer will be right is - as you say - unpredictable.
(And of course in a practical - rather than academic - sense you would only use that answer in a design where it was acceptable to have the output in that clock cycle be "probably 1" without any specification of how likely that was, or where there were no real consequences for potentially having the flip-flop enter a metastable state "for a while". Those applications tend to be more rare.)