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Since I'm (trying to work) in the saturation mode, the following formula should be valid:

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Since Vto is a static parameter it shouldn't change, same for K. And Vgs is 2 as determined by the voltage divider circuit. My DC operating point simulation confirms this. This leads met to believe that Id should be stable if you change the resister R1. However, according to the simulations this isn't the case. (Even though Vgs is 2, and Vds is higher than 2. My Vto should be 0 so I should be working in the saturation region) If I make R1 higher, Vds becomes lower and Id also becomes lower. Can someone explain this to me?

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  • \$\begingroup\$ Channel length modulation? Saturation current also increases with Vds \$\endgroup\$ – sarthak Jan 1 '18 at 12:27
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NMOS will be in saturation as long as: $$(V_{GS} - V_{TH}) < (V_{DD} - I_D R_D)$$ your formula for \$I_{DS}\$ will be valid only in this region. If you increase \$R_D\$, its obvious that at some point, the NMOS will come out of the saturation region and your formula for \$I_{DS}\$ is not valid anymore.

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Your Rd is 150 k ohm, that means that Id can never be more than 10 V / 150 kohm = 67 uA.

Now suppose the NMOS wants (according to the formula for Id) 100 uA to flow.

Who would "win"? The Resistor Rd or the NMOS?

I suggest that you do a DC simulation where you vary the value if Rd from 0 (zero) to 150 kohm and observe what happens to Id.

Only in the flat (horizontal) part of Id vs Rd will the NMOS be in saturation mode and will that formula for Id be valid.

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