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I've been for while looking to store a sampled data up to the rate of 30MBytes/s, an SD 3.0 host controller core in uhs-ii/uhs-i mode fits the requirements.

i'm not planning to buy SD full spec and i think it's quite possible to make SD 2.0 host controller core using just simplified spec, but is it possible to make SD 3 host controller in UHS-ii mode too? (SD Assoc offers uhs-ii simplified addendum, but is it enough?). Maybe it may not include some crucial details that would led me to a dead end.

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  • \$\begingroup\$ Welcome to EE.SE. As this is your first time using these terms could you please define what 'uhs-ii' means. \$\endgroup\$ – Sparky256 Jan 20 '18 at 4:00
  • \$\begingroup\$ Thank you @Sparky256 for your comment :-) for SD cards there are "rating speed" and "speed class". The latter is in the range [2,4,6,8 or 10 for SD 2.0] OR [uhs-i or uhs-ii for the SD 3.0] (e.g. sd 2.0 with speed class 2 has a minimum speed of 2 Mbytes/s and sd 3.0 with speed class uhs-ii (or better say in mode uhs-ii) has a minimum speed of 30Mbytes/s) hope i could explain it good for you :-) \$\endgroup\$ – SAADOV Jan 21 '18 at 9:07
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I read simplified spec and I think that it is sufficient to build the UHS-II host. Maybe some things are explained in a simplified way, but it is possible to check them on the builded prototype and improve it if they did not work.

The bigger problem is probably implementing this in FPGA. My favorite FPGA manufacturer, Lattice, not helping because requires a subscription license to use SERDES FPGAs (free license is only for non-SERDES FPGAs). I'll probably must switch to XILINX.

The commands look the same as in SD Legacy mode. Difference is mainly in the PHY, due to 8b10b and SERDES coding (and maybe in CRC to).

What FPGA do You plan to use for this?

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  • \$\begingroup\$ Welcome to EE.SE! Note that this site doesn't operate like a typical forum. Please avoid asking questions within your answers, as this opens the door for discussion. \$\endgroup\$ – Daniel May 17 '18 at 22:16
  • \$\begingroup\$ There's no reason most modern FPGA shouldn't be able to do the most of the faster speeds, with 1.8V IO the fastest SD switching rate is 208Mhz which isn't terribly fast for most midrange FPGAs... I doubt you even need the SERDES hardware which is mostly for implementing much higher speed interfaces like PCIe etc... \$\endgroup\$ – cb88 Dec 18 '18 at 22:28

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