I've been working on a 4-layer design built around the EFR32BG13 Bluetooth Low Energy SoC. While trying to measure the impedance of the antenna to build a matching circuit, I discovered that my short grounded coplanar waveguide (GCPW) transmission line was acting more like an antenna than a transmission line.

To narrow down the cause of the issue, I built a simple 4-layer transmission line test board, which is pictured here:

GCPW test board

The board is 100 mm square. I had these boards fabricated by ALLPCB, who specify 35 μm copper on all layers and 0.175 mm dielectric (dielectric constant 4.29) between the first two layers. Using AppCAD, I found that a design with 0.35 mm trace width and 0.25 mm gap yields an impedance of 48.5 Ω. The top layer for the board is shown in red above. The other three layers are ground planes that look like this:

Ground planes

I received the boards today and began by testing S21 for the second section from the bottom--a straight piece of GCPW with SMA connectors on either end. I used an HP 8753C / HP 85047A with a short length of coax connected to Ports 1 and 2 and the test board connected between those lengths of coax. Much to my surprise, this is what I saw:

S21 with GCPW

At 2.45 GHz, my transmission line has a response of -10 dB. If I replace the board with a "thru" connector, I see exactly what I would expect:

S21 with thru connector

I'm at a bit of a loss, as I thought that the first test would be a slam dunk and I would start finding issues with the more complex tests above it. I have a VNA and a strong desire to learn what I'm doing wrong here. Can you see any problems with my testing method or with the GCPW design itself? Any help at all would be greatly appreciated!

Edit: As suggested by Neil_UK, I have removed the thermals on one board by scraping away solder mask and then bridging the gap with solder. Measuring S11 and S21 with this configuration gives the following result:

S11 & S21 with no thermals

Comparing the S21 plot with the previous result, there does not seem to be any perceptible difference.

Edit 2: As suggested by mkeith, I have split one of the "strips" of my test board apart from the rest using the old "score and break" method. The board I chose to break off is the same board I removed thermals on, so this result is a further modification on the preceding plot. Here it is:

S11 & S21 with separated board

There is a deepening of the troughs in the S11 plot, but no significant improvement in the board's functionality as a transmission line.

Edit 3: Here is a photo of the board in its most recent embodiment:

Photo of GCPW test board

Edit 4: Close-up shots of both sides of one SMA connector:

Top side of SMA connector

Bottom side of SMA connector

The SMA connector is Molex 0732511150. The PCB land follows the recommendations in the datasheet here:


Edit 5: Here is a cross-section of the board near one edge:

Cross-section of board

The green lines are scaled from the manufacturer's specifications, which are copied here:

Manufacturer's specifications

Edit 6: Here is a top-down photo of the board with red scale lines showing the expected dimensions:

Top-down scale view of board

Edit 7: To verify the effect of the large center SMA land, I carved away the central pad on one board so that it was the same width as the rest of the trace. Then I used copper tape to extend the grounds on either side:

Narrow center land

Then I retested S11 and S21:

S11 & S21 with narrow center land

This seems to have improved S11 significantly, which leads me to believe that the large center land was, in fact, creating a capacitance at either end of the line resulting in resonance.

Edit 8: Looking for some guidance on how to handle the transition from SMA to GCPW, I came across this white paper:


While the paper specifically refers to the use of a high frequency substrate, I think much of it is still applicable here. Two main points stand out for me:

  1. The GCPW should continue all the way to the edge of the board.
  2. High frequency end launch SMA connectors use a center pin that is shorter and narrower to minimize its effect on the GCPW. These may be more appropriate for an application like this with a thin central conductor on the transmission line.
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    \$\begingroup\$ I am surprised, too. And not an expert in this area. But it looks like you put gaps in the GND plane, so that the grounds from the different test sections are not connected. Maybe the proximity of the next test section is somehow fouling things up. Can you cut the board so that there is only one test circuit? per board? You can cut PCB's with giant shears, if you have them. Or a dremel with a cutting wheel. \$\endgroup\$
    – user57037
    Jan 3, 2018 at 7:35
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    \$\begingroup\$ I can certainly try! I'll give it a shot tomorrow and edit my post with the result. \$\endgroup\$ Jan 3, 2018 at 8:00
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    \$\begingroup\$ And if possible, maybe measure S11 before you make any mods to the board. \$\endgroup\$
    – user57037
    Jan 3, 2018 at 8:18
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    \$\begingroup\$ There's something weird going on with the images; The ground plane isn't showing under the thermals of the edge connectors. It could just be a "feature" of the PCB software, but the ground plane is showing fine under the thermals in the topmost "strip". Also, I'm not an rf guy by any stretch of the word, so maybe it's perfectly normal, but is there really some really weird hatch pattern on the ground planes, or is that just a weird visualisation the PCB software uses for solid copper pours? Would it be possible to see the PCB backside, or better yet, the actual gerber files used for ordering? \$\endgroup\$ Jan 3, 2018 at 11:03
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    \$\begingroup\$ Looks like the S11 dips are separated by around 850 MHz. So the effective dielectric constant must be around 3.5 if I am not mistaken. \$\endgroup\$
    – user57037
    Jan 3, 2018 at 17:17

2 Answers 2


You should not use 'thermals' when grounding the SMAs. Those ground tabs should go straight onto the big unbroken ground plane. It won't even be harder to solder, the bulk of the SMA has to be heated up anyway, so there's no need for those three printed inductors in the ground of each SMA.

If you look at the ripple on your S21 plot, the repeating ripple is consistent with having poor match points spaced apart by your board width. That may not be the whole story, but sort out this obvious problem before looking for more subtle detail.

You don't need to get the boards remade, you can scrape off any resist and bridge the cuts with solder as a quick fix. Edit your post and add the new measurements when you've done that. BTW, S11 is usually a more sensitive measurement to make on 'expected good' thru lines than S21, though I agree, this S21 is pretty bad.

What's the board material (not an unimportant detail)?


So it's not the thermals, we are only at 3GHz I suppose.

Is the line calculated correctly? With those dimensions, this calculator gives 48.93, but it's obviously using zero thickness copper. This one gives 47.42 with 35um copper, and agrees with the other for zero thickness, so the design looks plausible. Those differences from what you have assumed are not enough to explain the measurements.

Is the board manufactured correctly?

The width and gap dimensions will be easy to measure with a microscope. The substrate thickness will be more difficult. The substrate dielectric constant even more difficult. FR4 \$\varepsilon_r\$ can vary depending on thickness and glass/resin ratio. Is the 0.175mm layer core, or pre-preg? Beware that pre-preg can vary much more than core when assembled, as the assembly conditions are not as well controlled as for the manufacture of core.

A capacitance measurement on a piece of board cut from your test board away from ground stitching vias will give you a combined thickness and dielectric constant. An electrical length measurement on your test pieces will give you essentially dielectric constant, with a small contribution from geometry.

It will be trivial for you to model a length of transmission line, and adjust length, impedance, and loss, until the simulated S11 and S21 match your measurements, you might even ask your optimiser to do that automatically for you. Is that a plausible model for your results?

I've suddenly noticed your signal tabs at the connectors are very wide, which will create a short length of very low impedance line at each connector, though at this length, modelling as a lumped C would probably be adequate to 3GHz. Add two lumped Cs to your model and try to fit those simulations to your results. Post an enlargement of the connector interface area so we can see what's happening there properly.


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    \$\begingroup\$ @MichaelCooper Updated my answer with more observations. I'm assuming that if you're using AppCAD you have an RF simulator as well. I'm particularly interested in the SMA interface detail. I can give other methods of measuring the line electrical length if you do need to get into that level of measurement. \$\endgroup\$
    – Neil_UK
    Jan 3, 2018 at 11:00
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    \$\begingroup\$ @MichaelCooper Yes, I'd estimate then that the tab is roughly 5mm long and 3mm wide, that's about 10ohm impedance. What's 5mm of 10ohm line going to do to your simulation? It's not going to radiate, but it may cause the line to resonate, and the increased energy stored in the line will result in increased losses, in the already very lossy FR4. This effect is known in RF circles as 'suck-out', at specific frequencies which hit resonance, all your power vanishes. \$\endgroup\$
    – Neil_UK
    Jan 3, 2018 at 11:09
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    \$\begingroup\$ @MichaelCooper I've had very bad experiences following recommended pad patterns, when the manufactuer doesn't know how it's used. You could relieve ground plane under it to reduce the impedance, perhaps by drilling from back? You could certainly use a scalpel to trim it down to the width of the tab. Neither are solutions, but experiments to help match simulation and experiment. Electrical length - cut the TX line in two places, each cut looks like 0.1pFish series, that gives you a weakly coupled \$\lambda/2\$ resonator and an accurate length, measure S21. \$\endgroup\$
    – Neil_UK
    Jan 3, 2018 at 20:03
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    \$\begingroup\$ @MichaelCooper That 3mm tab width is OK for a 1.6 thick board on microstrip, not for h=1/10th of that. \$\endgroup\$
    – Neil_UK
    Jan 3, 2018 at 20:06
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    \$\begingroup\$ @MichaelCooper Vinzent suggests in his answer removing the layer 2 ground just inside the connector. That means the ground is going up through long vias, which adds extra inductance. That's not a bad thing, it will help match the extra C, just very difficult to design. But it's probably preferrable to continuing the 350um track to under the connector and soldering it - very fragile. The thickness of the pin will reduce the impedance to the adjacent grounds anyway. Probably best to launch into 1.6mm thick microstrip, then have a designed transition to GCPW away from the connector. \$\endgroup\$
    – Neil_UK
    Jan 3, 2018 at 20:12

I think you interpreted the datasheet wrong, or rather you didn't account for the fact that you have 4 layers and ground on the top layer too, the design recommendations do not call for that with this layout.

enter image description here

It sayes "copper on bottom (ground) side"

This is how I interprete the datasheet;

The width of the center pad is designed to be well matched/ have close to 50ohm impedance when you have a 1.57mm thick DOUBLE LAYER (not 4 layer) board with ground plane on the bottom ONLY (~1.6mm below the track) that is why also if you look at the track going away from the terminal it is even wider that is because with a 1.6mm board with ground on the bottom only you need a very wide track to get 50ohm impedance.

If you have not removed the copper on the middle two copper layers below the center pad then you have moved the ground plane much much closer than it is suposed to be from the design specs. and also because you have ground on the top plane also you have changed the impedance from that as well. you distance between center and ground pads specified in the datasheet is not supposed to be filled with ground plane.

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    \$\begingroup\$ I see. Should the PCB lands basically be an extension of my GCPW, then? How much difference is this small a discontinuity likely to make at 2.45 GHz? \$\endgroup\$ Jan 3, 2018 at 19:53
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    \$\begingroup\$ It will most definitely make a big impact when your frequency is 2.45 GHz almost certainly what is causing your 10db insertion loss. \$\endgroup\$
    – user173292
    Jan 3, 2018 at 19:58
  • \$\begingroup\$ I think it might work if you as you say make the pad an extension of the track but you would have to try (: \$\endgroup\$
    – user173292
    Jan 3, 2018 at 19:58
  • \$\begingroup\$ I decided to do a "quick and dirty" test to see what would happen if I continued the GCPW into the connector. I've added an edit on my original post showing the results, which I think likely confirm the hypothesis that the center pad is creating resonance. \$\endgroup\$ Jan 3, 2018 at 22:35
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    \$\begingroup\$ Yes I saw your edit, glad you got it to work (:. But I think you will still get much better results when/if you make a new PCB because it is as you sayed only a "quick and dirty" and at 2.5GHz small stuff actually has an influence. \$\endgroup\$
    – user173292
    Jan 3, 2018 at 22:39

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