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The major steps of physical design that I learnt from a VLSI lecture are: 1)Partitioning 2)Floorplanning 3)Placement 4)Routing. The question of mine is about the steps 2 and 3.

It seems like the steps floorplanning and placement are somehow overlapping. We decide the places of the sub-blocks in floorplanning. But in placement step, we also decide the places of the sub-blocks and this time we take the interconnections into account too.

Placement step seems to be the expanded version of floorplanning. Then why do we have these two as seperate steps to be done one after another? Or should we think of them as a single step that are done interchangeably?

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  • \$\begingroup\$ Floorplanning: top-level, manual; placement: machine, places everything, using the manual floorplan as a starting point. \$\endgroup\$
    – EML
    Jan 3, 2018 at 13:50

4 Answers 4

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Floor planning can be considered your top level design and it may for example be guided by pin placement or interference between different modules. It is sensible to think about the overall design here; you may not want to place a sensitive analog component directly next to an RF oscillator.

Placement is then putting the gates within the overall plan. This may be fine first time round for a simple design, but it could be that your original floor plan does not, for example, allow all timing constraints to be met.

All the steps are related, so think of planning and placement as different levels of abstraction. It is usual to iterate through a number of designs to reach closure on all area and timing constraints.

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  • \$\begingroup\$ So, floorplanning can be considered as the placement method where your flexible(the sizes and shapes can still be changed) blocks are placed on your dice at higher levels. The method is only named placement when you are at a certain level(obviously the lowest level) and where the blocks are finally fixed(gates or fixed blocks), which means there are no other level of planning left and the placement occurs. The functionality of the two steps are similar but they change names according to the level of planning and flexibility of the blocks. Is that a good explanation do you think? \$\endgroup\$
    – packt
    Jan 4, 2018 at 14:46
  • \$\begingroup\$ Almost - at the floor planning stage, there's no detailed analysis of physical connectivity or timing, whereas during the placement stage this will be factored in. In floor planning, as a designer you're saying "I would like this module to be here for whatever reason", while in placement the software will try to optimise the actual location of the gates within the area you've specified. Then you miss timing closure and start again..! \$\endgroup\$
    – awjlogan
    Jan 4, 2018 at 15:02
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Levels of Abstraction. Floor planning is like designing the architecture of your house. Placement process is deciding what things have to be placed and where to place it inside your house.

For ASIC,

Floor planning typically includes :

  • Defining width and height of core and die.
  • Define the location of macros/pre-placed cells and corresponding decoupling capacitors.
  • Power planning and pin placement.

Placement covers the majority of the placement process

  • Binding the netlist with physical cells and placing it on the die.
  • Optimisation of placement of the cells on estimated wire length, keeping signal integrity.

  • Post Place timing analysis.

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Floorplanning : The stage where real design work happens (Port placement (Signal/clock/PG) , Power planning , Apt placement of fixed cells/blocks based on block shape and interacting ports ) .

See from above step we did placement of Macros/Pre-placed cells , what is left over ? Multi million cells !!

To place the left over multimillion gates we need very efficient placement algorithm that must be congestion aware ,timing aware and meets the power requirement.

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floorplanning is starts with creating physical only pad cells and defining their location and placing them. defining size and shape (by aspect ratio) of our block. defining PG pad rings for power continuity. specifying ignored routing layers , placing the macros by following some macro placement guidelines and defining the blockages. coming to the placement , here 1st will do some checks like placement setup checks, DFT and power set up checks and placing and legalizing the std cells and set up time optimization. In the summery, floorplanning is about placing the macros and blockages and leaving the uniform space for the std cells and placement is about placing and legalizing the std cells.

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