0
\$\begingroup\$

I'm having trouble solving these two problems (my solution and general solution showed): enter image description here

enter image description here

What I did was follow the truth table and based on the combination on the graph draw the appropriate state with a delay of 10ns: enter image description here

PLEASE HELP ME UNDERSTAND HOW TO DO IT AND WHERE I'VE GONE WRONG AS IM STRUGGLING TO DO THIS. Thank you in advance.

\$\endgroup\$
  • \$\begingroup\$ You do know what an SR latch looks like right ? google.ca/imgres?imgurl=https://sub.allaboutcircuits.com/images/… \$\endgroup\$ – Trevor_G Jan 4 '18 at 20:58
  • \$\begingroup\$ Yes. What do I deduce from that then? \$\endgroup\$ – Luca S Jan 4 '18 at 21:00
  • \$\begingroup\$ How many gate delays from the set pin to the Q pin? and from the reset pin to the Q/ pin? \$\endgroup\$ – Trevor_G Jan 4 '18 at 21:01
  • \$\begingroup\$ What do you mean? \$\endgroup\$ – Luca S Jan 4 '18 at 21:06
0
\$\begingroup\$

enter image description here

Note the path from Set to Q/ is only one gate delay, but from Set to Q is two gate delays. That is, when Set goes high, Q/ goes low one gate delay (10nS)later, which causes Q to go high one gate delay after that, for a total of 20nS.

Similarly, the path from Reset to Q is only one gate delay, but from Reset to Q/ is two gate delays.

You need to factor in those different delays into your timing diagram.

\$\endgroup\$
  • \$\begingroup\$ I get your point but I'm unable to visualize both in my mind and and paper how it would look. \$\endgroup\$ – Luca S Jan 4 '18 at 21:19
  • \$\begingroup\$ @LucaS Look at the first example in your question. Note Set goes high, and then Q/ changes to low 10nS later, then Q changes to high 10nS after that. That difference is because of the extra gate delay. \$\endgroup\$ – Trevor_G Jan 4 '18 at 21:36
  • \$\begingroup\$ So I've done the first example again from scratch as you said and it worked. I'll now do the second and let you know how it goes. \$\endgroup\$ – Luca S Jan 4 '18 at 21:39
  • \$\begingroup\$ I just have one question if I was in an exam condition, without solutions, I would look at the graphs to find the initial values of set and reset however to find the initial values of Q and Q\ what would I put (Q=0, Q\=1 or viceversa)? \$\endgroup\$ – Luca S Jan 4 '18 at 21:41
  • \$\begingroup\$ @LucaS it is normal to assume the startup condition is with the latch reset, that is Q low and Q/ high if there is no other information to the contrary. \$\endgroup\$ – Trevor_G Jan 4 '18 at 21:48
1
\$\begingroup\$

As Trevor shared the image in the comment, S-R latch contains NOR gates. In the first timing diagram, when S becomes 1, after 10ns QN becomes 0, and 10ns later Q becomes 1. Now, draw the S-R latch with NOR gates, write initial values near corresponding letters (S=0, R=0, Q=0, QN=1), change S to 1, and try to understand what changes you see. If you struggle, look at the timing diagram you shared.

\$\endgroup\$
  • \$\begingroup\$ I did as you said I changed S to 1 which has Q becomes 1 however looking at the first timing diagram the state of Q doesn't got to 1 but stays at zero. \$\endgroup\$ – Luca S Jan 4 '18 at 21:10
  • 1
    \$\begingroup\$ The diagram has been set according to delay of the NOR gate, which is the time the result of the NOR gate takes to perform. S and Q are 2 inputs of the NOR gate and the result of this gate is QN. Let say, when t=0 we change S to 1. When t=10ns, result of the NOR gate whose inputs are S and Q changes to 0. As you know QN is also input of the other NOR gate, so same delay story there too. 10 ns after QN becomes 0, the gate's output which is Q changes to 1. We have 2 gates each of which takes 10 ns to perform its task. \$\endgroup\$ – Jacob Warbler Jan 4 '18 at 21:17

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.