PLEASE HELP ME UNDERSTAND HOW TO DO IT AND WHERE I'VE GONE WRONG AS IM STRUGGLING TO DO THIS. Thank you in advance.
Note the path from Set to Q/ is only one gate delay, but from Set to Q is two gate delays. That is, when Set goes high, Q/ goes low one gate delay (10nS)later, which causes Q to go high one gate delay after that, for a total of 20nS.
Similarly, the path from Reset to Q is only one gate delay, but from Reset to Q/ is two gate delays.
You need to factor in those different delays into your timing diagram.
As Trevor shared the image in the comment, S-R latch contains NOR gates. In the first timing diagram, when S becomes 1, after 10ns QN becomes 0, and 10ns later Q becomes 1. Now, draw the S-R latch with NOR gates, write initial values near corresponding letters (S=0, R=0, Q=0, QN=1), change S to 1, and try to understand what changes you see. If you struggle, look at the timing diagram you shared.