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I have written a VHDL testbench to test a Verilog design. A lower level Verilog module instantiates some FIFOs through Altera Megawizard. The read FIFO code is below:

// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Sdram_RD_FIFO (
    aclr,
    data,
    rdclk,
    rdreq,
    wrclk,
    wrreq,
    q,
    wrusedw);

    input     aclr;
    input   [31:0]  data;
    input     rdclk;
    input     rdreq;
    input     wrclk;
    input     wrreq;
    output  [15:0]  q;
    output  [7:0]  wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
    tri0      aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

    wire [15:0] sub_wire0;
    wire [7:0] sub_wire1;
    wire [15:0] q = sub_wire0[15:0];
    wire [7:0] wrusedw = sub_wire1[7:0];

    dcfifo_mixed_widths dcfifo_mixed_widths_component (
                .aclr (aclr),
                .data (data),
                .rdclk (rdclk),
                .rdreq (rdreq),
                .wrclk (wrclk),
                .wrreq (wrreq),
                .q (sub_wire0),
                .wrusedw (sub_wire1),
                .rdempty (),
                .rdfull (),
                .rdusedw (),
                .wrempty (),
                .wrfull ());
    defparam
        dcfifo_mixed_widths_component.intended_device_family = "Cyclone IV E",
        dcfifo_mixed_widths_component.lpm_numwords = 256,
        dcfifo_mixed_widths_component.lpm_showahead = "OFF",
        dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
        dcfifo_mixed_widths_component.lpm_width = 32,
        dcfifo_mixed_widths_component.lpm_widthu = 8,
        dcfifo_mixed_widths_component.lpm_widthu_r = 9,
        dcfifo_mixed_widths_component.lpm_width_r = 16,
        dcfifo_mixed_widths_component.overflow_checking = "ON",
        dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
        dcfifo_mixed_widths_component.read_aclr_synch = "OFF",
        dcfifo_mixed_widths_component.underflow_checking = "ON",
        dcfifo_mixed_widths_component.use_eab = "ON",
        dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
        dcfifo_mixed_widths_component.wrsync_delaypipe = 4;

endmodule

The dcfifo_mixed_widths is something that is defined in the altera_mf library in my Modelsim. If this was a VHDL FIFO, I could just say library altera_mf; use altera_mf.all. However, since this is Verilog module, I cannot do so. However, I expect ModelSim to detect what is already there in a library called altera_mf.

When I start the simulation I get errors per FIFO saying "# ** Error: (vsim-3033) D:/Project/DE2_115_CAMERA/Sdram_Control/Sdram_WR_FIFO.v(70): Instantiation of 'dcfifo_mixed_widths' failed. The design unit was not found."

What is the workaround?

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  • \$\begingroup\$ Have you invoked ModelSim rtl simulation inside the Quartus after successful analysis and elaboration step which uses nativelink automatic approach to load/compile/map all the libraries or directly creating ModelSim project? You also have to specify test bench file in assignment -> settings -> simulation -> compile test bench -> add corresponding tb file \$\endgroup\$ – Sourabh Tapas Feb 4 '18 at 10:04
  • \$\begingroup\$ ok, I will try to do that I tried to replace those annoying verilog megafunction files with VHDL versions that I specified with same properties. However, that is not the best solution. The annoying part which I do not understand is that, Modelsim has the necessary files in its library. However, it says that it can't find them in this case. \$\endgroup\$ – quantum231 Feb 4 '18 at 11:17
  • \$\begingroup\$ I guess!, you need not have to replace the verilog files with vhdl versions if you have the mixed languauge modelsim version. \$\endgroup\$ – Sourabh Tapas Feb 6 '18 at 3:47

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