# Highly Distorted Output of Class B Power Amplifier

This is the circuit I made:

simulate this circuit – Schematic created using CircuitLab

This simple circuit incorporates differential stage - VA (Voltage-amplification) stage - OPS (Output Power Stage). Open loop gain is high, closed loop gain is approx. the value of 10. Miller effect of VA stage is compensated via Cc, which makes local feedback. Q4 is used for biasing of the OPS - when Vce = 2.4V, the current through Q6 and Q8 should be approx. 10 mA and the current through Q5 and Q7 should be approx. C1 is used for AC to bypass Q4 to be fed into base of Q7. 1 mA. Global NFB (Negative Feedback) is taken from the output and brought back to the non-inverting input of differential stage. I was first aiming for this amplifier to be loaded by 8 Ohm speaker but then changed my mind to 100 Ohm load, since there would be too high voltage gain drop (the current through last stage should be higher in my opinion). The current through Q3 and Q4 is approx. 10 mA, while collector currents through Q1 and Q2 are approx. 1 mA

Unloaded amplifier behaves as expected, but loaded amplifier has great amount of distortion in between its output signal. I cannot figure it out what is so wrong with this amplifier to produce such high amounts of distortion on the output.

This is the signal of unloaded amplifier versus loaded amplifier (5V per division):

What is wrong here stays a mystery for me but maybe you can figure it out.

Here is a little proof for the circuit I just made:

• Cripes, Keno! You are insanely busy at this stuff! My first comment, without looking at anything in detail, is that your output driver stage uses two quadrants of Darlingtons. Yuk! Use Sziklai, instead. And your VBE multiplier looks terribly wrongly arranged, just at a glance. – jonk Jan 6 '18 at 18:48
• That's not distortion, that's oscillation. Somehow you have built an AM radio transmitter. If it's all on a breadboard I'm not surprised it's unstable, but it's not going to be easy to fix by guesswork. Start by decoupling the power rails though. – Brian Drummond Jan 6 '18 at 19:25
• To start with, get rid of all of those ridiculous loops of jumper wire! No wonder it has enough parasitic feedback to oscillate! You should be able to lay this out on your breadboard so that 90% of the connections can be made using the component leads alone. – Dave Tweed Jan 6 '18 at 19:35
• @Keno The goal of Q4 is to keep the base of Q5 about 4*Vbe above the base of Q7. The thing to do this is called a Vbe multiplier. You don't have it set up right. – τεκ Jan 6 '18 at 23:43
• @Keno I discuss in the link I gave, but a problem with Darlington here is that you are talking about four VBEs to compensate for the VBE multiplier (Q4). The Early Effect is a bigger problem at 4X rather than 2X (as temp varies) and the temperature compensation parabola (needs a collector resistor) is more difficult to get right, I think. Also, with Sziklai you only need to worry about the temperatures of the transistors driving the main power BJTs, which is much much less of a problem than dealing with temp changes of the main power BJTs themselves. – jonk Jan 6 '18 at 23:58

I just quickly drew this up, the last hour or so. I agree that with wires on a protoboard such as what you are using, it's important to have lots of bypass capacitance right on the protoboard itself. Include that. However, I think you may also have had problems due to the fact that there is lots of capacitance (a few pF) between each nearby hole on the protoboard, too. And you didn't add some capacitance on the feedback resistor (which may be needed.) The values here are designed around the idea that you can deliver perhaps as much as $2\:\text{A}$ peak into an $8\:\Omega$ load, so I tried to take that into account. That said, I've really not done anything here but just "pop this out," quickly and roughly. No time for more than that.

simulate this circuit – Schematic created using CircuitLab

Here I set up the Sziklai output driver arrangement with the added $V_{BE}$ multiplier present as it should be. I've used two variable resistors, one keeping your $2\:\text{k}\Omega$ value (which I guess you have) and another being $100\:\Omega$. $P_1$ lets you adjust the quiescent current (which you can measure by checking the voltage between the collectors of $Q_{12}$ and $Q_{13}$.) $P_2$ lets you adjust things for temperature and Early Effect compensation. But feel free to completely remove $P_2$ and $R_3$ by shorting them out, if you want to. They are NOT critical. Just an offering. If you do ignore (short) them, then you may need to pick a different value for $R_2$ (smaller, perhaps.) You'll know if that's needed when you find you can't adjust the quiescent current to the right range with $P_1$. If so, pick a nearby value for $R_2$ and try adjusting $P_1$ again.

Feel free to ask questions, Keno. I'll try and answer them as I'm able to. To others, feel free to criticize and kibbitz.

Shoot for a quiescent current (no input signal) of perhaps one milliamp, or so. Adjust $P_1$ for that and read it off as I mentioned above. You can work out the voltage you'd need to read. (Feel free to increase the values of $R_{E_3}$ and/or $R_{E_4}$ to make it easier to pick this out -- just don't drop more than few tenths of a volt while adjusting things there.)

Assuming you need lots of current gain (and you do) for the output driver section, the Sziklai arrangement has a few advantages over the Darlington arrangement:

1. There are just two $V_{BE}$ drops to deal with.
2. These two $V_{BE}$ drops are subject to far less heating, so their $V_{BE}$ drops are more stable making it easier to plan the $V_{BE}$ multiplier behavior.

In the Darlington case, while it is still true that two of the four BJTs have less heating taking place, the fact is that it includes all four $V_{BE}$ drops in what is required to be controlled via the $V_{BE}$ multiplier. So this compounds the design of the multiplier or else decreases thermal stability. Either way, it's not a good thing in favor of Darlington. So one usually doesn't use it for cases like this.

(In short, I don't know of a good reason to use Darlington, other than part availability issues perhaps. So, for example, if high current PNPs are horrible and/or unavailable, you might replace $Q_{10}+Q_{12}$ with a Darlington alternative using only NPN. But you'd still probably keep the Sziklai on the bottom quadrant of the driver.)

Let's look at the current source stripped of some of the "extras." (They aren't important to understand the basic DC operation.)

simulate this circuit

Ignoring whatever load there might be for the $Q_5$ collector, you should be able to very roughly sketch out in your mind that this circuit will actually bias itself in some fashion. From $+20\:\text{V}$, there is a DC path through $RSET_1$, the emitter of $Q_5$ to its base, then through $R_{11}$, which is tied to ground. So there is no question that there will be some active current through that path. If $Q_6$ were pulled from the circuit, and assuming that $Q_5$ had a collector load to ground (or $-20\:\text{V}$) which didn't otherwise cause $Q_5$ to saturate, then we could compute the base current as:

$$I_B=\frac{20\:\text{V}-V_{BE}}{R_{11}+\left(\beta+1\right)\cdot RSET_1}$$

And this would be little different from the standard CE amplifier computation.

But in this case there is an added $Q_6$. What does it do? Before it is added, there is no particular limit to the voltage drop across $RSET_1$. It could be several volts, or more. But with $Q_6$ added, which is sensitive to its base-emitter voltage, any voltage drop across $RSET_1$ that is larger than about one $V_{BE}$ will cause $Q_6$ to source lots more current through its collector, all of which must be driven to ground via $R_{11}$. This added current causes an increased voltage drop across $R_{11}$. (Keep in mind that by adding only a mere $60\:\text{mV}$ to the voltage drop across $RSET_1$, the collector of $Q_6$ will source ten times as much collector current into $R_{11}$ which will mean also 10 times the voltage drop across $R_{11}$!) This increased voltage drop across $R_{11}$ also means that the base of $Q_5$ is pushed upwards (towards the positive rail) and this causes $Q_5$'s $V_{BE}$ to get "pinched", thus reducing its collector current.

What exactly is $Q_5$'s collector current? Well, it pretty much is the current in $RSET_1$. That's about it. And since we are also pretty certain about the voltage across it (one $V_{BE}$), we can compute the collector current in $Q_5$ pretty reliably. $Q_6$ will be constantly and carefully monitoring its own $V_{BE}$ and responding immediately to any changes by adjusting things at $Q_5$'s base and "pushing on/sinking current into" $R_{11}$ to make those changes work in the right direction.

In the end, there are about two $V_{BE}$ drops from your positive rail down to the base of $Q_5$. It's collector can "reach" about that high towards the positive rail before it starts saturating (causing other problems.) And this gives quite a lot of compliance range for the collector of $Q_5$. Which is a good thing.

In this short-hand version of the circuit found at the beginning of my answer, I removed $RB_1$. It's not strictly required for explaining the circuit. But it is added to help with possible oscillation when the circuit is part of a larger system and there is an AC signal being amplified. It doesn't drop much voltage, so you can "mostly ignore it." In general, a resistor of a few hundred Ohms to perhaps a thousand Ohms does the job, but the better value to use does depend on the base current (of course.) It's just not particularly critical-valued.

• Haven't got into details of you answer (I definitely will) but there is 150k base resistor for Q1 and Rf1 is 10k. Shouldn't they be of the same value for both of them so the base voltage is at approx. same level for both of Q1 and Q2? – Keno Jan 7 '18 at 10:57
• And I don't know if incorporation of current mirror at the collectors of Q1 and Q2 is a good idea, since I didn't quite understood what exactly happens there last time we discussed about it? – Keno Jan 7 '18 at 11:00
• @Keno All good questions! – jonk Jan 7 '18 at 16:11
• @Keno I'm leaving this discussion between you and G36, for now. I didn't worry about the Early Effect much in what I did. I also didn't do a lot of 2nd order effect thinking on the circuit. Your protoboard makes most of this not worth the effort, anyway. So I just did a "once over" and set it free. Don't fret the Early Effect that much, right now. There are some really BAD BJTs for this: the D45H11 (PNP) comes to mind. But by and large you can avoid the worry for now. Worry about it later when you care more about making improvements, not when getting things in a ballpark of working. NFB helps. – jonk Jan 8 '18 at 22:57
• @Keno In theory, let's say that Q10 and Q11 might need 1 mA, at most. (To simplify things.) And let's say that we set up Q7 to source 1 mA. Then, during peak output times all of the Q7 collector current would be "used up" before it gets to Q8. So Q8 would suddenly have nothing to do. But also, if it was Q10 sucking it up, then there would be nothing to "power" the VBE multiplier, either. This makes designing a predictable VBE multiplier and predicting the "average" load for Q8 impossible. Sure, you must accept variation. But you want to minimize that to some "reasonable" degree. 4 mA helps. – jonk Jan 10 '18 at 16:29

What you are seeing is not distortion. It is the amplifier oscillating at high frequency because +20/-20V have no bulk capacitance. This makes it so they have high impedance at high frequency due to the inductance of the wires going to your power supply and the power supply's limited frequency response.

Here's a simulation:

1uH is approximately the inductance of 1 meter of wire. The 100pF attached to the output could come from the stray capacitance of the breadboard.

Also: I redrew your schematic in a way that's a little clearer.

simulate this circuit – Schematic created using CircuitLab

• You could edit the question and put the new schematic in there. – JRE Jan 6 '18 at 20:39
• @JRE good idea. – τεκ Jan 6 '18 at 20:49
• I added those caps as you commented. And the output signal waveform changed to more sine alike but still incorporating oscillation signal within it. Then I started to move those jumpers in random positions (not connections but jumper's part connecting one end to other) and also the output signal waveform was changing. At some point (with amplifier loaded) the distortion disappeared and sinusoidal waveform was seen on the output of amplifier. – Keno Jan 6 '18 at 23:18
• @Keno You should observe the +20V and -20V with the oscilloscope. If they're not totally flat, add more capacitance. There's basically no such thing as too much. – τεκ Jan 6 '18 at 23:50

I didn't really read the whole question (too long, and didn't get to a clear point fast enough), but this is not what you seem to mean by "distortion":

This is very clearly the amplifier oscillating on its own when given a little kick by the input signal.

A brief look at the schematic shows why this shouldn't be a surprise. There is no capacitance on the power rails at all! The output is loading the power rails, which changes their voltage a little. That small change is picked up by the input stage, and then amplified thru the rest of the amplifier.

To fix this:

1. Put decent capacitance to ground on each power rail. This should be several 100 µF at least.

2. Break the power rails to the left of Q5 for the positive, and the left of Q7 for the negative. Put a small resistor in series, then followed by another few 100 µF to ground. This time, though, add some high frequency bypassing too, something like 10 µF ceramic to ground on each power line.

I think I remember telling you this before, but I don't feel like digging around in old history right now.

I think you are also told before that Darlingtons are not a good idea here. They require higher drive voltage than output, and have rather high saturation voltage. There are better ways, like using a power PNP for the top pass element of the final stage, then a power NPN for the bottom. Those can be driven by smaller NPN and PNP transistors, respectively. However, that is beyond the scope of this question.