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How can I shift whole my design using ISE(FPGAditor,plan ahead,..) to new placement? I want to no change in routing but change only in placement. Thanks.

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  • \$\begingroup\$ Welcome to the site. Please quickly realise that this is not a free design house, homework-answering service or an on-line technical encyclopedia, copied out to you on demand. People will help you take the next step if your question shows that you've done as much as you possibly could on your own - which your post doesn't, I'm afraid. Please revise your question showing your work and findings so far, in considerable detail. Or delete the question if Internet searches give you your answer anyway. Again, a warm welcome to the site. \$\endgroup\$ – TonyM Jan 7 '18 at 9:52
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    \$\begingroup\$ Erm. You can't. If you change only the placement and not the routing, nothing would be connected anymore. \$\endgroup\$ – Tom Carpenter Jan 7 '18 at 10:02
  • \$\begingroup\$ I want to no change in my design routing. I want to pick up my design and put it in an other location of FPGA. \$\endgroup\$ – anna martin Jan 7 '18 at 10:27
  • \$\begingroup\$ @annamartin What problem do you have that requires you to move a design around inside an FPGA? \$\endgroup\$ – Harry Svensson Jan 7 '18 at 10:46
  • \$\begingroup\$ I want to see different features(power, delay,...) in different location with fixed routing in my design and just change in placement. \$\endgroup\$ – anna martin Jan 7 '18 at 10:51
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Your question relates very specifically to particular features and architectural parameters for a certain FPGA. You should be directing this question directly to the support engineers at the FPGA manufacturer. If your endeavor is one of an educational research type you may find that there are support folks from the manufacturer that will want to help out.

Also note that what you are proposing to evaluate is not going to be able to be done with a generic design module that uses an end to end tool flow. In fact I suspect that the FPGA manufacturer will guide you to build test configurations that map directly to a specific part architecture. Such test configurations would only use a very specific subset of the development tool chain and the circuit realization in the configuration will be rather simple.

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You probably can, using placement constraints (RLOCs - Relative Location Constraitnts) on your module.

A module synthesised to a "black box" can then be placed with one LOC constraint and all its RLOCs are offset from that. I would start by synthesising it and opening it(after Mapping) in PlanAhead, to floorplan it as you want.

The attraction was experimental results that promised a speed improvement from 80MHz to 120MHz on a Spartan-3, by floorplanning a specific critical component.

HOWEVER.

When I tried this years ago, the tools were ISE (3.1 up to 6.x) and Floorplanner, and this aspect of them was demonstrably so buggy (multiple interacting bugs) as to be utterly unusable - a mixture of generating illegal placements and rejecting legal ones.

After all the workarounds, it transpired that placing multiple instances of the component, routing density increased and some of the speed increase was lost. The result was simply not worth the manual effort involved, given all the bugs.

It may or may not have improved since those days, but you can expect to do a bit of pioneering to find a process that actually works as advertised. Good luck with that, and I look forward to hearing a success story.

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