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I'm designing a single side pcb, due to trail's density, I decided to use link wires in order to avoid overlap, but when I started routing, the software didn't allow me to connect any wire to link's pad. I tried to assign some netclass but couldn't find a way to that. Sometimes, only by luck, I successfully make the connection, but I'm clueless about what made it possible. I attached a picture that illustrates both situations. I'm using Proteus 8.6 SP2.pcb layout with link(jumper) connection

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After we switch from ISIS to ARES, Proteus creates a netlist with information regarding the pads interconnection. This information is graphically represented with green lines once the components are placed in PCB layout. Those green lines are called Ratsnest. The manual states:

The term Ratsnest is used to describe the pattern you get on the screen when the pin to pin connections specified in the netlist are shown as single straight lines rather than copper tracking.

If using autorouter, ARES will generate copper tracking only between pads with ratsnest connection.

In this problem, a manual routing is being performed. ARES will use the ratsnest to assist the user in the routing process, it won't let a connection be made between two pads that don't belong to the same net, the same is true for a pad without a net. The former case is what is preventing us to connect the trace and the link's pad.

The link is a component that only can be generated inside ARES, but as long as the netlist is generated with the information provided by ISIS, ARES won't allow us to create any trace with the link, once the schematic doesn't give any information about it.

Thus, we need to include the link's pad to a specific net and then create our route, according to this procedure:

  1. Select the Ratsnest Mode (Red Rectangle);

enter image description here

  1. Click in link's pad;
  2. Click in a pad belonging to the same net in which the link should be connected;
  3. If you have done this right, you will see a ratsnest (green line);
  4. Now select the manual route and create a trace;

Although this could be seen as an issue, this behavior really helps avoiding accidental connections in layout, specially in large PCB's.

I recommend reading this page before using the Ratsnest Mode.

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  • \$\begingroup\$ Please, be kind and notify me from any grammatical mistakes, English isn't my mother language. \$\endgroup\$ – Oshio Feb 4 '18 at 4:59
  • \$\begingroup\$ I don't fully understand your method, since I haven't used ISIS and ARES. However, it sound like it requires several manual steps for each link, and probably breaks the link between the schematic netlist and PCB connectivity, so you won't be able to do a DRC check between schematic and PCB. Designing the PCB as if it was two layers, and minimizing the tracks (which will become links) on one layer will require manual routing to minimize the number of links, and to locate the vias for the ends of the links as required, but will not break the link between schematic netlist and PCB, so you ... \$\endgroup\$ – Peter Bennett Feb 4 '18 at 7:11
  • \$\begingroup\$ ...can do a DRC between schematic and PCB, and get useful results. \$\endgroup\$ – Peter Bennett Feb 4 '18 at 7:13
  • \$\begingroup\$ I've done some testing after reading about the your feedback about the DRC check issue and here is my conclusion: In the Ratsnest Mode, Proteus won't allow the link to be connected to two different nets, when one link's pad is assigned to some net, the other one automatically will be attached to the same net. I belive this behavior exists to avoid breaking the bond between schematic and layout, therefore the DRC and CRC remain valid. \$\endgroup\$ – Oshio Feb 4 '18 at 20:30
  • \$\begingroup\$ Just to remember that this is valid for the component "link", I'm pretty sure that what @Peter mentioned will be valid for almost any other component like resistors, capacitors, transistors, etc... You will mess up with the CRC and DRC functionalities. \$\endgroup\$ – Oshio Feb 4 '18 at 20:34
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Design the board as two-sided, with vias large enough to accept the link wires. I would try to make any tracks on the "link" side straight, as they will be replaced with wire links on the finished board.

If you design the board as single-side in the PCB program, you will need schematic symbols to show the links, along with a variety of footprints to cover the various lengths (and shapes) of links you have.

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  • \$\begingroup\$ You are right @Peter, your method works and indeed is what almost every one in my research have recommended. But i came to a solution that I think is simpler, although I don't know if it have any drawbacks. What are your thoughts about the method I proposed? I would like to see your feedback. \$\endgroup\$ – Oshio Feb 4 '18 at 5:13

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