What does influence of routing in static/dynamic power consumption in FPGA design?
I want to know that, different routing results different power consumption?
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There will definitely be effects. Longer wires have more capacitance that will need to be charged up on every transition, increasing power consumption. Generally the place and route tools will attempt to make the wires as short as possible in an effort to minimize delay. There could be variations in the static power consumption of routing components as well, though this would be extremely architecture-dependent.
Yes, with each trace on the PCB there will be parasitic resistance and inductance.
The problem is FPGA's have a lot of gates that switch at the same time (even amps of current can be drawn from some FPGA's), this results in the load increasing and the demand for current increasing on very short timescales. This causes a voltage drop at the power pins on the FPGA. If the voltage drop is to great, the gates will not be powered and output 'noise' instead of the correct voltage for a 1 or a 0 which will result in an error in a Boolean calculation.
PCB traces are simply conductors, every conductor has resistance (which causes a voltage drop) and inductance (which prevents current from moving from one place to another immediately). This contributes the voltage at the FPGA to drop.
What can you do about it? There are two ways to combat this problem:
1) Make sure you have sufficient power filter capacitors. Power filter capacitors provide a short term storage next to the FPGA to combat line inductance.
2) Make sure the voltage drop through PCB traces is small enough for the current moving through it. The first thing you will need to do is find a PCB trace calculator that can estimate the resistance of the trace. Then estimate the current needed by the FPGA, most provide a tool or a spreadsheet (like Xilinx) that can estimate the current.
If your FPGA needs at most 1A, and it the pcb trace is 0.100Ω then this would result in a 0.1V drop (V=I*R). This may not be acceptable for a 1.2V or 1.5V design, check the FPGA datasheet for limits on power. If you increased the trace size by 5x then you would only have 0.020Ω and a 0.02V drop.
An FPGA, at least the Xilinx ones I've used, has a variety of routing resources.
Clock distribution is optimised for high speed clocking, and covers the entire chip. This is used preferentially for clocks by the PAR.
Data has a number of different lengths of line. Some go LUT to LUT for very local connections, fast carry chains for instance. There are so-called 'long lines' that cross the die, which can be broken into small sections to limit dynamic power consumption, or routed right across. There are also several types of intermediate length line. All of these will have different dynamic power consumption.
The PAR will select from the available resources to meet timing constraints. With a sparsely populated die, it might be possible to anticipate what will get used for what. With a dense design, where the PAR struggles, it will be difficult to guess what it's going to use for what.
This means that only the post-layout reports will give you accurate estimates.
There is only so much you can do to control power dissipation from interconnect, once you have done the obvious things of arranging adders in columns, putting logic next to its IO so you don't cross the chip, using the dedicated clock buffers and so on, the obvious stuff. Basically if the PAR is to meet timing constraints, then it has to use what it uses.