I am loading the image of my Spartan 6 and it seems that it cannot go to the final step of the process: the "Startup Sequence". After I load the image byte by byte, and add a lot of extra clock cycles at the end, the status register of the FPGA reveals that there have been no errors, and GHIGH STATUS status being high means that:

The device has properly received its entire configuration data stream. The device is ready to enter the Startup sequence.

I have checked that the INITB and PROGRAMB are not pulled low preventing the startup sequence, and in the status register everything looks very promising.

Why is my Spartan 6 not entering the startup sequence after it received and is happy with the image?

(Below is the status register after configuration.)

[0] CRC ERROR                                                              :         0
[1] IDCODE ERROR                                                           :         0
[2] DCM LOCK STATUS                                                        :         0
[3] GTS_CFG_B STATUS                                                       :         0
[4] GWE STATUS                                                             :         0
[5] GHIGH STATUS                                                           :         1
[6] DECRYPTION ERROR                                                       :         0
[7] DECRYPTOR ENABLE                                                       :         0
[8] HSWAPEN PIN                                                            :         1
[9] MODE PIN M[0]                                                          :         0
[10] MODE PIN M[1]                                                         :         1
[11] RESERVED                                                              :         0
[12] INIT_B PIN                                                            :         1
[13] DONE PIN                                                              :         0
[14] SUSPEND STATUS                                                        :         0
[15] FALLBACK STATUS                                                       :         0

Solved it! The problem turned out to be that I was using the JTAG clock for the startup sequence, rather than CCLK. The choice of clock is specified inside the "Startup Options" inside ISE.

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