avr adc differential mode frequencies

Question

I know that in single ended free running mode the following equation holds:

f_ADC = f_clk/N = 13f_s

where f_ADC is the ADC frequency, f_clk is the avr's clock frequency and f_s is the sampling rate.

The above equation means that if I want to convert an analog signal with a max frequency of 4KHz then I should choose f_s=8Khz (Nyquist theorem), and then choose N such that f_ADC >= 13fs=13*8KHz.

Now, I've read in the ATMega128 datasheet that in case of differential channels gain (eg to convert the difference of two analog signals), an internal f_ADC2 frequency is produced which is f_ADC2 = f_ADC/2 (or is it f_ADC2 = 2*f_ADC ????) but can't really figure out what happens with timings.

So the actual question is: what equation holds (like the one above) if I use differential gain channels at free running mode?

Answer 1

From page 235 of the datasheet:

Differential conversions are synchronized to the internal clock CKADC2 equal to half the ADC clock. This synchronization is done automatically by the ADC interface in such a way that the sample-and-hold occurs at a specific edge of CKADC2. A conversion initiated by the user (i.e., all single conversions, and the first free running conversion) when CKADC2 is low will take the same amount of time as a single ended conversion (13 ADC clock cycles from the next prescaled clock cycle). A conversion initiated by the user when CKADC2 is high will take 14 ADC clock cycles due to the synchronization mechanism. In free running mode, a new conversion is initiated immediately after the previous conversion completes, and since CKADC2 is high at this time, all automatically started (i.e., all but the first) free running conversions will take 14 ADC clock cycles.

This is the only paragraph where they talk about CKADC2. It's nowhere mentioned in the electrical characteristics either. Overmore, the table preceding this paragraph says 13 ADC clock cycles for single ended conversions and 13 or 14 for differential, also "conversion time (cycles)". It looks like the same ADC clock is used, and that CKADC2 is only relevant for that 14th cycle if a conversion is started when CKADC2 is high.