I'm using a single PIC16F18857 as an I2C master to talk to five PIC16F1615's on the bus. All is working great, for the most part, however, I've been experiencing a "lock up" where the master is stuck in a loop waiting for a read to complete. I managed to catch it on the analyzer and here's what I'm seeing:
The third signal is an async UART input to the master PIC16, I was trying to see if the timing of it with relation to the was somehow related, but I've seen nothing to support that so far.
There are currently only two slaves on the bus, and the read always fails during the read to the first slave.
What's curious to me is that the master (which is controlling the clock) seems to stop clocking the slave after three clock cycles (I'm seeing three cycles consistently) and I'm missing an interrupt -- most likely because the clock sequence is not finishing all of its cycles. I would be less puzzled if the clock was being held low by something, but it seems the clock is stuck in the "unasserted" high state.
Under what circumstances may this happen?
- I have checked the silicon errata for both parts, nothing that pertains to this issue is listed for either part
- I've tried to see if its correlated with another peripheral interrupt firing, none of the data I've collected seems to point to that being an issue