I have a very basic question about VHDL. Do we need a separate .ucf file for each .vhd file or not? The reason I am having many .vhd files because each of the entity specifies a different interface. Should I combine all of them? For example, I am working on SPI interface of the FPGA to configure a chip, and LVDS interface of the FPGA to read output from the chip (just for higher data rate). Therefore, right now, I am having 2 .vhd files for each interface. Is that correct? Any recommendation on which document to read would be appreciated. Thank you.
All components are usually integrated into a single top level entity. It would be the final "wrapper" VHDL file which defines all ports, generics and all of the entire design. This is the HDL file which is then synthesized. So one UCF file is enough, which is defined only for this top level module.
You can refer to synthesis guides from Altera or Xilinx website.
From the Xilinx UG903, page 8 (note: this is Vivado not ISE but should still apply):
Xilinx recommends that you separate timing constraints and physical constraints by saving them into two distinct file s. You can also keep the constraints specific to a certain module in a separate file.
Typically, I will have a single project wide timing constraints file and a single physical constraints file. Then if I have any large components that I plan to reuse in other projects I will create individual timing constraint files for them.