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I've been toying for a few months with the GO board to start getting some bases on how programmable logic works.

I've managed to get through pretty easy stuff and the basic one byte UART, here's where my dilema and frustration begin. How the hell can i implement a simple function in my UART module to send a multibyte stream?

It'd be nice (maybe it's not the way you're supposed to work with FPGAs) to be able to have a function and pass the text/value to output via UART as a parameter.

Is it possible (of course almost everything is possible) to do such thing in a nice, handy way? Am i too wrapped up in the microcontroller mindset and this is not feasible?

Can someone outline me the structure to do it?

Thanks,

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  • \$\begingroup\$ Why don't you share to work you have actually done? To hardcode a string in a FPGA, I think your best option would be to store it into FIFO. I can't tell how the interface between your UART transceiver would work as I do not know how your transceiver work. Usually, these type of trnasceiver works bytes by bytes with a signal indicating that the last byte is gone (sometimes with double buffering). Maybe a state machine transferring data form the FIFO (or any RAM structure) into the transceiver would be the way to go. When designing in HDL you need to think in terms of electronic components \$\endgroup\$ – Pier-Yves Lessard Jan 9 '18 at 19:42
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    \$\begingroup\$ The distinction between writing software that's executed by a CPU and designing a digital logic circuit with VHDL is an important one to recognise - the difference is vast. Please don't make the beginner's mistake of trying to write a program in VHDL :-) You're best served by (a) understanding digital logic circuit design and then, only then, (b) understanding how to design these logic circuits in VHDL. I imagine you may just want quick results but there's tons on the interweb on all this for free. Good luck with it all. \$\endgroup\$ – TonyM Jan 9 '18 at 20:50
  • \$\begingroup\$ @ Pier, The FIFO route seems the way to go indeed, i'll read about them and see if i can program one and it's testbench! @TonyM, If i wanted quick results i'd have asked for a chunk of code :P, As you said, i'm in the process of understanding the nature of digital logic, it's uses and how to get the mindset to work with this tech. \$\endgroup\$ – Aleix Jan 10 '18 at 7:46
  • \$\begingroup\$ That is exactly the right approach and fantastic to hear, Aleix. As a start, in VHDL it's 'design one', not 'program one' - you have no CPU to run a program on :-) Think digital circuits all the way, VHDL is essentially a glorified schematic. Have fun, please post future findings and ask more. \$\endgroup\$ – TonyM Jan 10 '18 at 9:08
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There's a lot of digital design concepts you'll need to know to do this. I guess an outline would be:

  1. Design a finite state machine that shifts out a single 10-bit serial frame (assuming 8-N-1 so one start bit, 8 data bits, 1 stop bit). The module accepts a clock (your baud rate) and some 8-bit data, as well as a "go" (start shifting data) input and "done" (all bits shifted) output indicator.

  2. Design a baud rate generator module that produces your clock of say 9600 baud. This will probably be some kind of counter that you'll compare to a value to know when to toggle the baud clock output and reset the counter. Its input will be whatever clock sources are available on your FPGA board, probably something in the MHz range.

  3. Design a FIFO module for storing data to be transmitted serially. The FIFO has data in, data out, a clock and reset, and status flags for full and empty.

  4. Design another state machine that unloads data from the FIFO and transfers that single byte to the shifting-out module you previously developed. This way when the FIFO is full, it will send out new characters until empty. It will need to examine the FIFO empty flag to know when to start and stop.

  5. Make a top-level module that loads some data into the FIFO. Maybe your development board has buttons or switches to accomplish this, you can load in a binary word at a time to the FIFO and then press a button to make the FSM start outputting data byte by byte.

At every step you need to write a test bench module and validate all aspects of the module you are testing. It's a critical part of development even though some people put it off until the end.

I'd read up on state machine design to get more information. You need to know about Mealy and Moore type state machines, how the control unit (FSM) controls a data path which operates on data, etc.

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  • \$\begingroup\$ Hi CM, you're proposing FSMs as if they're the obvious and only way here but they're the last thing I'd advocate using. FSMs serve decision-making paths of operation. But (1) is a fixed sequence, so would be a bitrate CLK prescaler and a shift register. And (4) is just two when-else's, not an FSM. OP doesn't "need to know about Mealy and Moore type state machines" at all. Downvoting, if this text is changed/removed will happily remove dv. \$\endgroup\$ – TonyM Jan 10 '18 at 7:03
  • \$\begingroup\$ @charles M, Thanks! Actually the transmitter is modelled using a FSM, some LED's from the board to indicate idle, TX status, etc.. and a button to enter the TX sequence. The baud rate generator is pretty much the the same approach you're suggesting! The FIFO module seems a convenient way (and not overly complicated) to store and serve the data to the UART module, i'll take a look into it :) \$\endgroup\$ – Aleix Jan 10 '18 at 7:40
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    \$\begingroup\$ @TonyM: OP is learning about programmable logic so this is a good opportunity to introduce fundamentals that will help with future projects. \$\endgroup\$ – user171804 Jan 10 '18 at 15:41
  • \$\begingroup\$ Very true indeed but that's not the point I made. FSMs? \$\endgroup\$ – TonyM Jan 10 '18 at 17:25

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