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I would like to use a single pin (tri-state buffer, 3.3V logic in case this matters) to drive two P-channel MOSFETs as high-side switches. Only one of them will be 'on' at any time. When the pin is in the high-impedance state (hi-Z), I would like both turned off.

The solution I came up with is to pull-up the hi-Z state (to 0.2*Vcc, see comments) and use two comparators (open collector type) to drive the FETs when the pin is in either the Lo or High state:

schematic

simulate this circuit – Schematic created using CircuitLab

I wonder: is there a better, easier or more elegant approach to this? Is this solution suitable for fast switching?

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    \$\begingroup\$ Honestly, the intent of this circuit is clear and the part count isn't terrible. I'd keep it unless you have a PCB space constraint requiring you to reduce it. Even then, I'd just try to select smaller parts. \$\endgroup\$ – pgvoorhees Jan 10 '18 at 12:53
  • \$\begingroup\$ Tri-state detection may be of interest. \$\endgroup\$ – Transistor Jan 13 '18 at 18:42
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    \$\begingroup\$ @Jens If an IO pin on an MCU is left floating at mid voltage you could damage the pin due to excessive current draw in the input buffer. See ti.com/lit/an/scba004d/scba004d.pdf . You must make sure that the biasing resistors leave the undriven pin voltage above VIH (typically either 2.0V or 0.7*VCC). \$\endgroup\$ – user4574 Jan 14 '18 at 23:29
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    \$\begingroup\$ @user96037 Good point. My MCU has VIH(min)=0.75VCC and VIL(max)=0.25VCC. So a 4:1 or 1:4 divider / keeping the pin at 0.2VCC or 0.8VCC should avoid the excessive current in the pin and the comparators can use a 1:4:1 divider for the window. \$\endgroup\$ – Jens Jan 15 '18 at 4:37
  • \$\begingroup\$ Related: Tri-state input detection circuit, Patent US 6133753 A \$\endgroup\$ – Jens Jan 17 '18 at 18:10
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Hmm, maybe this isn't more elegant per say...

This can be solved by making a PMOS based inverter and an NMOS based inverter. An NMOS based inverter will invert a voltage around the threshold voltage for the NMOS, this voltage will be different for the PMOS based inverter. If both NMOS and PMOS transistors have threshold's that is less than half of VDD, then you will get a voltage range in between where both are inverting. That means in the following cases that neither of the output is on.

Here's one solution that only requires 4 transistors:

enter image description here

Here's the link if you want to interact with it. It's outputs are not two P-mos transistors, but this can be solved by adding a 5th transistor.

The reason for why I decided to share this schematic is that maybe your construction in space-limited, then this might be a good solution.


The upper graph is the voltage at the gates of the leftmost transistors.
The middle graph is the voltage across the upper load.
The bottom graph is the voltage across the bottom load.

A schematic, with 5 transistors, that works "ish" as you described would look like this:

enter image description here

Here's the link for this schematic.


The upper graph is the voltage at the gates of the leftmost transistors.
The middle graph is the voltage across the upper load.
The bottom graph is the voltage across the bottom load.


Here's the "ish" part from above:

Bleh, just realized that this only works if your output pin is within the output voltage stage VDD. So this design won't work with 12 V since your pin is probably only between 0 and 3.3/5 V. Oh well.


Edit

Here's a schematic... that will do what you want, but honestly, it's just messier than your solution. Unless you make your own custom ASIC with these transistors and internal resistors / current sources.

enter image description here

Here's the link for this schematic that


The upper graph is the voltage at the gates of the leftmost transistors.
The middle graph is the voltage across the upper load.
The bottom graph is the voltage across the bottom load.

With this solution, it works with 3.3 V and uses the logic inverters as level shifters as well.

But if I were you, I'd go with the solution you've come up with on your own. But with LM393 instead of LM319 because I'm a cheapskate and LM393 has somewhat smaller footprint (fewer pins).

But if high speed is what you need, then LM319 is the job for you, obviously, or my transistor/resistor solution with 1 kΩ instead of whatever 10k/100k they have now.

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  • \$\begingroup\$ Thanks for the suggestion. I like the symmetry: The Vgs thresholds of the two left transistors 'hardcode' the comparator window and the middle transistors replace the open collector outputs :) It's probably worth saying that, in absolute terms, the left transistors maximum Vgs threshold values need to be lower than the input's minimum Vcc/2! \$\endgroup\$ – Jens Jan 10 '18 at 16:41
  • \$\begingroup\$ I don't know if this is legit... simulation - what do you think? \$\endgroup\$ – Jens Jan 11 '18 at 15:12
  • \$\begingroup\$ @Jens "If both NMOS and PMOS transistors have threshold's that is less than half of VDD, then you will get a voltage range in between where both are inverting.". Meh, I was sloppy saying the Vcc/2. Oh well. That simulation is not dumb at all, I'd definitely try it out on a bread board if I were you. - This is probably the "worst" question I've ever answered. Worst in the sense that the person asking the question had two answers that were better than mine. \$\endgroup\$ – Harry Svensson Jan 11 '18 at 16:00
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Inspired by Harry's reply, here's a solution that requires 3 resistors and a BJT transistor (plus the usual two N-channel MOSFETs and pull-ups to drive the P-channel MOSFETS). Input and output voltages are independent, e.g. you can control 12V from a 3.3V MCU or 5V from 5V logic:

schematic

simulate this circuit – Schematic created using CircuitLab

Simulation link above won't work, click here instead

Notes:

  1. In the Hi-Z state, R1/R2 pull-up the input voltage and must be adjusted so that "Test" is

    (a) sufficiently lower than M1's gate threshold voltage to keep it cut off. For 2N7000, this should be less than 0.8V; and

    (b) lower than the pin's maximum VIL to prevent excessive currents in the controller. For ESP8266, this is 0.25*Vcc, or less than 0.825V when running at 3.3V.

  2. In the HIGH state, the pin's output voltage must be sufficiently higher than M1's gate threshold. For a 2N7000, this should be at least 3V. Slightly lower voltages will probably work as well.

  3. The switched voltage (here: 12V) must be sufficient to fully turn on M3/M4. For the FQP27P06, you'll need about 8V. Select logic level MOSFETs if you need to switch lower voltages.

  4. For Q1, pretty much any NPN will do (e.g. 2N3904 or BC547). Pull-ups R3..R5 can be 10K, less if you need to switch at higher frequencies.


For a low side switch, get rid of M3/R3 and M4/R4 and connect your load directly to M1 and M2, probably upgrading them to something more suitable:

schematic

simulate this circuit

Simulation link above wont't work, click here instead.

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