I've done ICs where the onchip crosstalk between widely differing frequencies (2.6MHz, 13MHz, 65MHz from Prescaler, to 2,400MHz in offchip VCOs) needed to be -100dBc.
I achieved that, first pass, by placing 10pF MIM metal-insulator-metal capacitors at the end of each row of the FracN frequency synthesizer logic.
And placed a 100 Ohm onchip resistor between the logic and the VDD pin.
And mechanically designed the capacitors for high self-dampening.
The 2.6MHz spur was -105dBc, the lowest the "customer" had ever seen.
Additionally, on a 23/24 prescaler, having my control over how package pins were used, I dedicated 3 sets of VDD/GND to that prescaler, and achieved loadpull of the external VCO of -120dBc. Whereas the "Can we please reuse this
16/17 prescalar? We trust it." having only 1 set of VDD/GND pins, was shockingly bad in the load-pull (-90dBc, from vague memory).
Fundamentally, in placing systems on chip, if you want controlled low spurious, you need to plan and think and worry.
I was told, after the first-pass-success in meeting all the measurable specs,
that obviously the chip was very easy. Because it was first-pass-success.
I simply stared at the high-level manager (not in my command structure) and said
"You will never know how many hours I spent thinking and modeling and writing up
ways to achieve isolation."
Part of the success in low crosstalk came from using differential current-mode interfaces into the FracN logic core, and using differential current-mode out of the logic core to the PLL UP/DOWN charge pumps. Which has nothing? to do with onchip bypass capacitors, right? Nope. The differential current-mode interfaces operated at constant current thus no VDD sags were generated and the other circuits (as well as the substrate) were spared the glitches.
What does this mean? As the chip designer, you can PLAN the various cross-domain and cross-frequency interfaces for minimum vulnerability (differential!) and minimum trash-generation (differential, again). In some cases, you can avoid onchip charge-storage, because your charge demands become more constant.
What system performances improve, with this planning? SHMOO plots improve.
And deterministic-jitter improves; beatnotes are reduced, and phase-lock pulses become very small upon lock, with no squirrely hunting around the null-point, because the charge-injection variation is set by thermal noise in the dividers and the PFD and charge-pumps and not by deterministic charge battling.
What is the advantage of very small (very narrow width) in-lock pulses in a PLL?
The thermal noise and 1/F noise and any power-supply noise, from the current-sources or other charge-control circuits, is attenuated because the ONtime is much less. Thus the entire phase-noise plot versus offset-frequency now has the opportunity to further reduce, because the broadband noise injection is reduced, because the UP and Down pulses are very narrow; full height but very narrow.