I'm a newbie to electronics, so apart from the obvious physical size issues there may be a clear reason as to why this is a dumb question, but if the general rule of thumb is to use a bypass capacitor for all ICs on a board, why not just build capacitors right into the components? Is there a reason this never became a standard feature?

Sure, there's a size issue on smaller ICs (especially SMD chips and the like), but in a lot of applications vertical height doesn't seem to be an issue and it would simplify circuitry and BOMs etc.

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    \$\begingroup\$ It is not only a size issue, but a material issue. Basically, it is much cheaper to NOT include them on most packages. I have seen flip-chip BGA's with capacitors on them, though. They were so expensive that adding capacitors was not a cost issue. \$\endgroup\$
    – user57037
    Commented Jan 10, 2018 at 5:56
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    \$\begingroup\$ Note: at least you can get DIL sockets that have capacitors integrated (e.g. between pin7 and pin14 for DIL-14 sockets, or between pin8 and pin16 for DIL-16 sockets that fit for many logic ICs) \$\endgroup\$
    – Curd
    Commented Jan 10, 2018 at 8:35
  • \$\begingroup\$ Not every IC needs a bypass capacitor on its own, sometimes about 2 to 5 ICs in close distance may share the same capacitor. It depends on the ICs and the application. \$\endgroup\$
    – Uwe
    Commented Jan 11, 2018 at 11:27
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    \$\begingroup\$ I hate to ruin the fun, but Why aren't decoupling caps built into the IC or IC package? \$\endgroup\$ Commented Jan 11, 2018 at 13:47
  • \$\begingroup\$ @DmitryGrigoryev I did actually search and failed to find anything... good catch. \$\endgroup\$
    – Matt Lacey
    Commented Jan 11, 2018 at 23:21

4 Answers 4


The last time I got a quote to add capacitors or resistors to a chip it was about $0.01 per part to be added plus the cost of the part. Parts like say an Intel/Altera/Xilinx FPGA, or a processor usually have decoupling capacitors built in and then also require some on the PCB as well. It's a complex question that depends on the part and application.

If you're making a $1.00 microcontroller and you've added $0.10 worth of capacitors that is going to put you at a price disadvantage at the negotiating table (despite your competitor needing $0.10 of parts on the board!). Additionally there is a constant push now for smaller and smaller packages. Adding large 0201 01005 parts is not helping. Then also adding parts lends itself to packages that have a substrate board. Lots of cheap little parts are using leadframes with no good way to solder parts to it. Some parts are now coming in CSP packaging which is essentially just the die. No place for external decoupling caps there (more on that later).

The other thing is your part may not need it, but sometimes it will. The connection between the die and the board could be many things, a bond wire to a substrate, flip chip to substrate, leadframe, etc. This path has an impedance (and inductance) that resists your die's desire to pull current through it. When you're a big power sucking chip with high frequency current demands like an FPGA or CPU you may not be able to pull the kind of current you want without significant voltage drop. Placing capacitors on your substrate and bypassing that impedance is more about robust functionality at your operating frequencies than it is about convenience for the pcb designer.

Finally chips do actually include bypass capacitance right on the die. A lot of things wouldn't work if we didn't. Now those structures are small of course and not the 1uF you can get with a discrete part. However they all work together to provide a stable voltage where it matters at the actual circuit on the die. Your on die capacitance is the first line of defense, followed by your on package, followed by your pcb board. But you can see that by the time you reach the board you've already gone through quite a bit of impedance so your 1uF 0402 may not be effective enough for that highspeed bit of logic. So then you need some die capacitance maybe, but oh maybe you can't get enough without blowing up the area (and thus the cost) so then you start thinking about putting in some on package caps. Then you start obsessing about lowering the package impedance (inductance again) so maybe you don't need quite so many on die parts...

Long story short it's a tradeoff like everything else we do.


The bypass capacitances on the order of 0.1uF are too large for silicon processes used for creating ICs. Metal-oxide-semiconductor (MOS) structures are used to create capacitors inside the ICs. These structures create capacitance with density on the order of 100pF/mm2.

further reading:
Chapter on MOS capacitors
Similar question on Research Gate, if you have an account there


It's possible to do this in expensive parts like desktop CPUs (and where there are real benefits in performance) and Stratum 3 clock modules, but the cost of including MLCC capacitors in IC packages is something few manufacturers would pay for. There is little market for non-SMD parts that are not high power and don't have an insane number of contacts.

Capacitors of appropriate value cannot practically be made as part of the IC chip itself, so it would have to be extra bits. See Nick's answer for why this is usually impractical.

Back in the Paleolithic era of socketed DIP parts, there were sockets offered with MLCC caps between the usual corner power pins, but I don't think they were very successful in the market.

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    \$\begingroup\$ Spehro, what process is used in the expensive parts which you mention in the first paragraph? Or, would that be done by co-packaging ceramic capacitors next to silicon? \$\endgroup\$ Commented Jan 10, 2018 at 6:18
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    \$\begingroup\$ @NickAlexeev The caps are added to the package generally these days on the bottom side. The process would just be to solder them onto the package. cdn.wccftech.com/wp-content/uploads/2013/04/… \$\endgroup\$
    – horta
    Commented Jan 10, 2018 at 6:27
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    \$\begingroup\$ @NickAlexeev The former are Flip-Chip on HDI PCB substrate with the heat spreader on top and the decoupling caps on the bottom inside the contact pattern, eg. i5, i7 high end CPUs. The latter are ceramic hybrids with the caps soldered to the top surface outside the hermetic cover. There may be parts with caps right on the lead frame- I think some of the RS-232 drivers did that for the charge pump caps. CPU: goo.gl/images/7YBPAX \$\endgroup\$ Commented Jan 10, 2018 at 6:28
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    \$\begingroup\$ I understand that high end Xilinx devices (Kintex for instance) have bypass devices on the package. \$\endgroup\$ Commented Jan 10, 2018 at 9:31
  • \$\begingroup\$ @PeterSmith The EVM for the Xilinx Zynq has some insane number of ceramic bypass capacitors - maybe 300 (and many relatively high value- some as much as 100uF). Not all associated with that one chip, but enough of them are. \$\endgroup\$ Commented Jan 11, 2018 at 6:13

I've done ICs where the onchip crosstalk between widely differing frequencies (2.6MHz, 13MHz, 65MHz from Prescaler, to 2,400MHz in offchip VCOs) needed to be -100dBc.

I achieved that, first pass, by placing 10pF MIM metal-insulator-metal capacitors at the end of each row of the FracN frequency synthesizer logic. And placed a 100 Ohm onchip resistor between the logic and the VDD pin. And mechanically designed the capacitors for high self-dampening.

The 2.6MHz spur was -105dBc, the lowest the "customer" had ever seen.

Additionally, on a 23/24 prescaler, having my control over how package pins were used, I dedicated 3 sets of VDD/GND to that prescaler, and achieved loadpull of the external VCO of -120dBc. Whereas the "Can we please reuse this 16/17 prescalar? We trust it." having only 1 set of VDD/GND pins, was shockingly bad in the load-pull (-90dBc, from vague memory).

Fundamentally, in placing systems on chip, if you want controlled low spurious, you need to plan and think and worry.

I was told, after the first-pass-success in meeting all the measurable specs, that obviously the chip was very easy. Because it was first-pass-success. I simply stared at the high-level manager (not in my command structure) and said "You will never know how many hours I spent thinking and modeling and writing up ways to achieve isolation."


Part of the success in low crosstalk came from using differential current-mode interfaces into the FracN logic core, and using differential current-mode out of the logic core to the PLL UP/DOWN charge pumps. Which has nothing? to do with onchip bypass capacitors, right? Nope. The differential current-mode interfaces operated at constant current thus no VDD sags were generated and the other circuits (as well as the substrate) were spared the glitches.

What does this mean? As the chip designer, you can PLAN the various cross-domain and cross-frequency interfaces for minimum vulnerability (differential!) and minimum trash-generation (differential, again). In some cases, you can avoid onchip charge-storage, because your charge demands become more constant.

What system performances improve, with this planning? SHMOO plots improve. And deterministic-jitter improves; beatnotes are reduced, and phase-lock pulses become very small upon lock, with no squirrely hunting around the null-point, because the charge-injection variation is set by thermal noise in the dividers and the PFD and charge-pumps and not by deterministic charge battling.


What is the advantage of very small (very narrow width) in-lock pulses in a PLL? The thermal noise and 1/F noise and any power-supply noise, from the current-sources or other charge-control circuits, is attenuated because the ONtime is much less. Thus the entire phase-noise plot versus offset-frequency now has the opportunity to further reduce, because the broadband noise injection is reduced, because the UP and Down pulses are very narrow; full height but very narrow.

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    \$\begingroup\$ +1 Interesting. ~160MHz cutoff. Are there actually mechanical effects at MHz frequencies on-chip? \$\endgroup\$ Commented Jan 11, 2018 at 6:12
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    \$\begingroup\$ Ahhhh --- I designed the aspect ratio so the ohms//square gave me the desired sqrt(L / C) for Q+2, zeta=1 dampening. And I kept the 30 squares-ohm of the metallization in mind, in chosing on which two sides to connect to the capacitor. And used a number of vias to stitch the metallization onto the capacitor. In other words, I did some sketches and mechanically designed (performed thoughtful layout) of the caps. \$\endgroup\$ Commented Jan 13, 2018 at 3:37
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    \$\begingroup\$ Regarding the"Spehro Pefhany" comment: there were at least 10 rows of gates/FFs in the FracN logic, thus at least 20 capacitors, thus at least 200pF. Which makes F3dB 160/20 = 8MHz. With lots of local dampening. \$\endgroup\$ Commented Jan 23, 2018 at 17:14
  • \$\begingroup\$ @ Spehro Pefhany Yes there are "mechanical effects" at MHz frequencies onchip--- the Thermal Timeconstant of a 1 micron thick junction (or other bit of silicon) is 11.4 nanoSeconds, or about 13MHz F3dB. The thermal timeconstant of 10micron cube of silicon is 100X slower, at 1.14microseconds. The thermal timeconstant of 100micron cube is 10,000X slower at 114uS. \$\endgroup\$ Commented Mar 17, 2018 at 15:35

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