I have this design I grabbed online, and when I load it up in eagle and run a DRC, it gives me a bunch of airwire errors on vias that appear to serve no function. Are they just ones the designer left on there and don't care about? Is there any other possible reason why they still exist?

Here's one where there's one directly under IC1.


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    \$\begingroup\$ Maybe it's supposed to connect to internal planes that somehow got removed? \$\endgroup\$ – DerStrom8 Jan 10 '18 at 12:23
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    \$\begingroup\$ One of the functions of theratsnest command is to actually generate any polygons. Did you run it before doing DRC? Also, give us the link to the original design, so we can see whatever documentation came with it. \$\endgroup\$ – Dave Tweed Jan 10 '18 at 12:32
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    \$\begingroup\$ When trying to show us routing, make sure all the copper layers are on, and get rid of the clutter. Don't show the soldermask, and the layer that causes all those hole symbols to be drawn. That lets us more easily see the routing you are asking about. Can you post the .BRD and .SCH files? Those would answer a lot of questions, and would allow others to show you samples of how to achieve certain things. \$\endgroup\$ – Olin Lathrop Jan 10 '18 at 12:36
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    \$\begingroup\$ Whoever did that board never had it manufactured. Just looking at the traces I doubt that it would pass a DRC from any board house (at least any I've used). The traces look to be less than 5 mils, the via's are too close to the pad (not necessarily bad, but can make it difficult to solder without filling the via). Also 3V0 might be a mistake, most electronics are 3V3 and it has unnamed nets (N$2). I would do some serious rework before having this board made. \$\endgroup\$ – Ron Beyer Jan 10 '18 at 15:48

First, airwires are not errors. They show connections specified in the schematic but that have not been realized in the board. They represent work not done yet, not mistakes necessarily.

In this case, unless you are not showing us all the copper layers, the via under IC1 makes no sense. If it is not a deliberate thru-hole pad for some purpose (not in the schematic), and it is not part of a larger structure in additional hidden layers, then it serves no purpose.

If the above is really the case, then the routing is a mess. Run away. I see several other vias that appear to serve no purpose from what you show. If this really is the case, then you should rip up the whole mess and route the board properly yourself.


Just for entertainment, I looked at the board and schematic files. Yikes! What a mess!

Run away. This tiny board and schematic would be far easier to generate from scratch properly that it would take to fix this disaster. Whoever designed this was incompetent. Some obvious problems:

  1. There are several pads too close to the edge of the board for most ordinary board house processes. I loaded my own standard DRC settings for a two layer board, and it found 10 such cases.

  2. One of the pads is too close to a hole. This is in the upper right-ish area of the board. The pad is connected to ground.

  3. Many of the pads are partially covered with stuff from the tDocu layer. This makes the board difficult to work with in routing, and it serves no useful purpose. For example, every pad of the 44 pin package seems to have a deliberate tDocu rectangle covering the inner ⅔ or of each pad. This makes no sense, and prevents using tDocu for legitimate purposes during routing.

  4. The gratuitous vias that you are actually asking about are apparently due to a misguided attempt to put a partial ground plane on both sides of the board. The vias are to stich the two sides together. A much better strategy is to try to use one side, in this case the bottom, for a ground plane as much as possible.

  5. The board is offset to some strange value from the origin. There is no point to that.

  6. I didn't really look at the circuit, but that single 100 nF bypass cap for all four power pins of the microcontroller is a joke. Even worse, it's not even placed by any of the power pins. And then it's right in the middle of the densest part of the board, getting in the way of other routing.

As a quick challenge, I took the board you provided, ripped up all the routing, and defined the bottom layer as a ground polygon. I then connected most ground pads directly to the ground plane with their own vias. That freed up a lot of routing complexity on the top layer.

I also moved the single lone bypass cap to the top power and ground pin pair of the micro, and connected the other three power pins to that in a star as much as possible. This is not the right way to do this, but I was just trying to get past that to see what routing of the whole board would look like.

After manually routing the ground, and the microcontroller power connections, I let the auto-router do the rest. Here is the result:

The next step would be to clean that up a little, minimize the size of islands, etc. There is certainly obvious opportunity for some cleanups.

Anyway, the point is that the board you have was incompetently designed. I didn't really look at the circuit, but the schematic is also messy. Given the messy schematic and downright irresponsibly designed board, there is little confidence in the circuit.

Find out who made this mess and avoid anything else by the same person. Run away!

  • \$\begingroup\$ brd sch Are the eagle files. I wanted to modify it to add a reset button, but when I use dirtypcb DRU file, there's lots of errors. And the image I posted has all the layers turned on. \$\endgroup\$ – Oggie Jan 10 '18 at 17:41
  • \$\begingroup\$ I should also add that the gent who modified this got it from zip and here \$\endgroup\$ – Oggie Jan 10 '18 at 17:47
  • \$\begingroup\$ thanks for all the help and tips. You're way more experienced at eagle than I am. It'll take me forever to get this cleaned up. Starting from scratch seems like it would even take longer. \$\endgroup\$ – Oggie Jan 10 '18 at 20:10
  • \$\begingroup\$ @Ogg: Not ditching this mess and doing it right would take even longer and be more expensive in the long run. \$\endgroup\$ – Olin Lathrop Jan 10 '18 at 21:07
  • \$\begingroup\$ are you suggesting that I reuse the schematic, but redo the brd from scratch? \$\endgroup\$ – Oggie Jan 11 '18 at 0:17

See what net it is connected to?
I'ts used for Ground plane stitching. You are missing a copper pour/ground fill polygon on at least one of your layers. EDIT: So, either it's not generated/poured, or it has somehow been deleted from the layout.

  • \$\begingroup\$ Right on. Probably connecting a pour to an inner plane \$\endgroup\$ – DerStrom8 Jan 10 '18 at 12:30

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