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i tried the to figure the what is this gate but i coud not it seems to pass one or high impedance on positive clock depending on the input and zero or high impedance on negative clock

put i can't figure it's type nor pass transistor realization

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original image

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    \$\begingroup\$ Hint: give the node in the middle a name like "mid" and add it to the truth table. Then think what happens when the clock toggles. \$\endgroup\$ – Bimpelrekkie Jan 10 '18 at 13:47
  • \$\begingroup\$ Can you see any NAND's? and TG equivalents? \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jan 10 '18 at 13:59
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This circuit has 2 binary inputs, so only 4 possible input states. That's a small enough number of states to start out by solving them exhaustively, like by using a truth table.

Start with that and see what you get, then report back.

Added

It's good that you've noticed that sometimes the result is high impedance. Now think what that means for the internal node. Due to capacitance, the internal node will stay as it was last driven, at least for a little while.

Also note that this is really two identical gates in series, just that each is presented with the opposite polarity of CLK. This should be a clue you are looking for some kind of latch or flip-flop behavior.

Analyze what happens with the four possible combinations of input high and low, and rising and falling edge of the clock.

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  • \$\begingroup\$ that what i did i got that if the clock 1,input 1 output 1 clock 1 input 0 high impedance clock 0 input 0 out 0 Clock 0 input 1 get high impedance put i don't no what is this gate \$\endgroup\$ – A_S Jan 10 '18 at 15:55
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In other words, reduce the schematic to logic symbols and redraw.

Consider it as a finite state machine( FSM) with 2 inputs with 4 combinations and 2 transitions or edges of each input with outputs (0,1,no change)

Then change the schematic from a transistor switch to TG's and compare counts of Q's.

It simplifies to a common logic circuit and teaches you how they are actually made.

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Here's another hint: How does the following circuit differ from the given one?

schematic

simulate this circuit – Schematic created using CircuitLab

Note that both versions are examples of dynamic logic; a purely static analysis won't tell you much.

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