I am looking for a specific type of latch or flip-flop or "black box circuit" that will give a constant low output until it receives an input pulse, and will then go high and stay high regardless of the input until it either it receives an enable signal on a separate line or the input stays low for X clock cycles.

Please note that in both cases, the clock signal shown would not actually be provided to the circuit! It is included as a reference for understanding the timing, the circuit itself only receives the signal (and possibly the enable) and needs only the indicated output.

Option A (Signal/Enable):

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So the output goes high on the first signal pulse rising edge when the enable is high, and stays high until the enable goes low again regardless of what the signal does. The first signal pulse is ignored because the enable is low. The second pulse triggers the output to go high. The third pulse has no effect because the output has already been triggered.

Option B (Single-input):

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Here the output goes high on the first received signal pulse, and stays high until it goes through 3 full clock cycles without receiving any signal, at which point it goes low. The first pulse triggers the output. The second pulse has no effect because the output has already been triggered. The rising edge of the 5th clock cycle sets the output to low because it is the 3rd cycle with no signal.

That is the general problem I am trying to solve, and I am more than happy with a general solution - a particular type of latch that will do this, or a combination of latch types that will do this. A specific solution that requires input voltages, latencies, etc. is nice but not expected and may not be worthwhile if I cannot provide the needed details. Regardless, here are the details I can provide:

This is a proof-concept project with minimal budget primarily using available lab equipment, and the attempt is to produce the circuit at minimal cost - this is more likely to be bread-boarded than to have an actual board etched. Ergo, board space is not a concern, nor is flexibility - I am trying to jury-rig a workaround for one piece of lab equipment. The system consists of a number of separate instruments that are being manually operated, so the time between event "A" and event "B" may not be a function of the hardware but of how long it physically takes me to get from one instrument to another and flip a switch.

The single-run operating time for this system is up to 4 hours, so ideally this latch will stay high for that long!

The signal is being provided by a lab signal generator operating at 6kHz with 7us square pulses. There is no separately available clock signal - when the signal generator is enabled (push-button) the signal starts, when it is disabled the signal stops.

If there is going to be an enable, it is going to be manually-operated switch or push-button, and so the enable and disable may happen at any point in a clock cycle.

Supply voltages can be as needed, although I would like to keep the number of supply voltage to a minimum for practical reasons. I currently have a couple of 15V supplies that power a galvanometer in the system, I can either voltage divide off that or bring in a separate power supply.

The signal and any enable should be reliably within 0-0.2V low and +/-0.2V of the supply high. The outputs should be between 0-0.8V low and 2.7-5.0V high, presuming that I will be using 5V TTL downstream.

The timing is complicated by the human in the loop. Although I showed enable timing in the diagrams, I would anticipate that the circuit would be enabled prior to the arrival of the first pulse. From the rising edge of the first triggering pulse, the output should go high within 80us (the diagrams show a 10us delay). The output reset time is inconsequential, as the lack of signal will already have disabled any sensitive components elsewhere.

For the single-input option, any clock signal needed to trigger the reset would need to be internally provided, and allow for the reset to happen within a second of the signal end. As mentioned before, the clock illustrated is not actually available, it is simply being used to produce the signal. The purpose of the reset is simply to avoid having to cycle power to the circuit when it is necessary to start the process over again. The combination of clock frequency and number of pulses needed to reset the circuit is inconsequential so long as it is >333us and <1s.

Further timing issues are difficult to address at this time because the only extant parts of this system use the 6kHz signal and aren't digital. This latch will interact with a demux and possibly a delay line, but those have not been specified at this time.


As an alternative, a latch that only went high for 10-150us once until was enabled would ALSO work. That is, on receiving the first pulse, it goes high for 10-150s and then goes low until it receives some external input from a manual push-button or such. Said latch could start in the high or low state so long as it went high long enough to cover the 7us pulse with some tolerance for timing errors and jitter, and went low thereafter until reset.

Please let me know if there are any questions or suggestions.


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    \$\begingroup\$ Second version, your description is incorrect, the second pulse DOES have an effect, it increases the time before the output clears. This is called a retriggerable monostable. \$\endgroup\$ – Brian Drummond Jan 10 '18 at 18:22
  • \$\begingroup\$ Sounds like a retriggerable one-shot to me, but I am concerned about the X clock cycles variable. IS that a fixed rate clock? Does the output need to be synchronized to that clock somehow? \$\endgroup\$ – Trevor_G Jan 10 '18 at 18:32
  • \$\begingroup\$ @Brian Drummond, thanks for the correction! From what little I know of retriggerable monostable devices, once they receive the input pulse they go high for some period T defined either by the device itself or by an R/C timing circuit, correct? Out of curiosity, do you know how long the output pulse can be set high by such a device? My system is ideally going to operate continuously for up to 4 hours after enable, so ideally I would want the output to remain high for at least that long. \$\endgroup\$ – cosmicfish Jan 10 '18 at 18:35
  • \$\begingroup\$ @Trevor_G, the "fixed number of clock cycles" is in reference to the system clock that (outside the signal itself) this circuit won't be able to access. Once the signal stops, it cannot count signal clock cycles anyway. So the real issue is that it cannot go low again during a single signal cycle (~167us) and ideally won't go low for at least twice that. But the timing has to be achieved internally. \$\endgroup\$ – cosmicfish Jan 10 '18 at 18:39
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    \$\begingroup\$ ... non-retriggerable latch and wait for some uspecified act of god to flip the bits for you into the reset state. Presumably your actual needs fit somewhere between these two unreasonable extremes. \$\endgroup\$ – Cort Ammon Jan 10 '18 at 19:15

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