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I know that if both transistor in a cmos inverter are enhancement then the output will be as shown in the figure: enter image description here

But I wonder, what if one of them is enhancement and the other is Depletion?

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  • \$\begingroup\$ Do you understand the difference between a depletion and enhancement MOSFET? Also, what is Vin1 and Vin2. Ditto Vo1 and Vo2? \$\endgroup\$ – Andy aka Jan 11 '18 at 12:50
  • \$\begingroup\$ I do understand the difference between them. Vo1 is the inverter output for input Vin1, Ditto Vo2 and Vin2 \$\endgroup\$ – Bakr Hesham Jan 11 '18 at 12:55
  • \$\begingroup\$ How can you expect to get -5V out of a circuit that has only a positive supply and ground? \$\endgroup\$ – Finbarr Jan 11 '18 at 14:36
  • \$\begingroup\$ Sorry , i missed to indicate that -Vss=5 voltages, in the second state \$\endgroup\$ – Bakr Hesham Jan 11 '18 at 15:02
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But I wonder, what if one of them is enhancement and the other is Depletion?

If, in the top picture, M1 was a depletion mode MOSFET, to turn it off you would need a gate voltage significantly lower than 0 volts. This means that a depletion MOSFET used in this type of complementary circuit would be ON for a greater range of the input voltage span and for a greater period of time both MOSFETs would be ON and conduct (potentially) a lot of current from the positive supply rail to ground. This of course is normally to be avoided.

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  • \$\begingroup\$ I know that it is avoided, but what will the output be then? \$\endgroup\$ – Bakr Hesham Jan 11 '18 at 13:08
  • \$\begingroup\$ If the transistion of Vin from positive 5 volts to (say) -5 volts was quick (to avoid MOSFET destruction) and the power supply could provide the instantaneous current surge as Vin changed then the output would be the same as using two enhancement MOSFETs. \$\endgroup\$ – Andy aka Jan 11 '18 at 13:19
  • \$\begingroup\$ Ok this makes sense, then what about 0 to 5 vlots? \$\endgroup\$ – Bakr Hesham Jan 11 '18 at 13:37
  • \$\begingroup\$ With an input of 0 to 5 volts, the MOSFET that was a depletion type would never turn off - it's gate has to go a few volts below 0 volts (N channel) or above 5 volts (P channel) to turn it off. \$\endgroup\$ – Andy aka Jan 11 '18 at 13:45
  • \$\begingroup\$ So could we say that the output will be approximately 2.5 to 0 at D-nmos , 5 to 2.5 at the D-pmos? \$\endgroup\$ – Bakr Hesham Jan 11 '18 at 13:49
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If one transistor is of the depletion type, then that transistor will never switch off. That transistor is then effectively a variable resistor.

In the case that the NMOS is a depletion type and the PMOS is an enhancement type mosfet, the output voltage can still easily reach 0V at an input of VDD. The PMOS is still able to completely shut off current, leaving just a conductance to ground.

Reaching VDD with the output at an input of 0V however will not be possible anymore. You get into a situation where the NMOS and the PMOS will "fight" over the output voltage using their currents. If the NMOS is conducting more than the PMOS then the NMOS will "win" and be able to pull the output downwards. If the PMOS has a very high transconductance, then it will "win" and the output will be pulled more upwards.

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  • \$\begingroup\$ Could we deal with them as two resistances, thus at a D-nmos , if the input is 0 both E-pmos and D-nmos will conduct , then by assuming that both have the same internal resistance then both will have the same voltage drop so the output will be 2.5v \$\endgroup\$ – Bakr Hesham Jan 11 '18 at 14:27
  • \$\begingroup\$ Yes, however the I-V relations are very nonlinear so it's not easy to say where exactly it will end up. If you wish to know the point more accurately, you'd have to make some figure like fig. 7.13 in link. \$\endgroup\$ – Sven B Jan 11 '18 at 14:35

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