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So how do I calculate maximum frequency if this values are given: \$T_{Hold-ff}=0.2ns\$, \$T_{Delay-ff}=2ns\$, \$T_{Delay-nor}=0.3ns\$,\$T_{Delay-nand}=0.4ns\$,\$T_{Setup-ff}=0.5ns\$.

I thought about: \$T_{Delay-ff}=2ns\$+\$T_{Delay-nor}=0.3ns\$+\$T_{Setup-ff}=0.5ns\$

Is that good?

Also how could I calculate Response time (time from the clock edge on the clock until output A, B, C)?

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The data launched by the third flip-flop has to be captured by the first flip-flop in the next clock cycle for correct functionality. The path is Q out-> NOR -> AND -> J in . Also it is the critical path here. So the maximum frequency of operation would have to satisfy:

$$T_{Delay-FF}+T_{Delay-Nor}+T_{Delay-Nand}+T_{Setup-FF} < T_{clk}$$

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  • \$\begingroup\$ Why don't you use hold time of flip flop? What about my second part of question about this time until outputs? \$\endgroup\$ – Alen Jan 11 '18 at 16:18
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    \$\begingroup\$ If you correctly understand what is hold time you will see that hold time is irrelevant in calculating maximum frequency of operation, as it puts no limitation in the clock period of the design. Setup time is defined between two consecutive clock edges in flip-flops and hence it puts limit on clock period. But Hold time is defined on the same clock edge of launching and capturing flip-flops therefore the clock period never comes into picture. Only delays and clock skew come into picture there. \$\endgroup\$ – Mitu Raj Jan 11 '18 at 16:27
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    \$\begingroup\$ edn.com/design/systems-design/4392195/… -- explains well \$\endgroup\$ – Mitu Raj Jan 11 '18 at 16:29
  • \$\begingroup\$ Can you help me with second part of this question so I could accept your answer? \$\endgroup\$ – Alen Jan 11 '18 at 16:47
  • \$\begingroup\$ Second part is not clear to me. Do you mean rise time or transition time of outputs? \$\endgroup\$ – Mitu Raj Jan 11 '18 at 16:49
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No after the clock edge you have Tdelay-ff to get an output from the ff worst case you need to add Tdelay-nor to that and also Tdelay-nand. this signal needs to be at the input of the first flop T-setup before the next clock edge. So the minimum period is Tdelay-ff+Tdelay-nor+Tdelay-nand+Tsetup-ff

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  • \$\begingroup\$ Why don't you use hold time of flip flop? What about my second part of question about this time until outputs? \$\endgroup\$ – Alen Jan 11 '18 at 16:18
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    \$\begingroup\$ The time to valid outputs is Tdelay-ff I said that. Hold time is the time the input to the flip flop has to remain stable after the clock for the ff to work properly as this 0.2nS and Tdelay-ff is 2ns it is irrelevant to the question. \$\endgroup\$ – RoyC Jan 11 '18 at 16:22
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To calculate the maximum clock rate of this circuit, one must understand the impact of each delay on the Q output, especially the 1st stage.

If the Hold time is less than any other delay, it can be assumed that this condition is always satisfied.

However all other delays will affect the total setup time for JK inputs so the answer for period of the maximum clock frequency is the sum of all other delays;

T = Q3 delay + NOR delay + NAND delay + Q1 setup delay
= 2+0.3+0.4+0.5 = 3.2ns or f ~ 312 MHz

part 2) ABC outputs all have only \$T_{Delay−ff}=2ns\$ after Clock edge

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  • \$\begingroup\$ Why don't you use hold time of flip flop? What about my second part of question about this time until outputs? \$\endgroup\$ – Alen Jan 11 '18 at 16:18
  • \$\begingroup\$ Since all other delays > T_hold, that condition is as good as T_hold=0 so it is not added. \$\endgroup\$ – Tony Stewart EE75 Jan 11 '18 at 16:19

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