I am trying to configure a chip over SPI interface using FPGA Spartan 6 Eval board. I just need to configure, I do not need to read the data from the chip, it will be done by another interface. Therefore, I want to send constants to register values of the chip. Errors I got are:

Line 59: Cannot update 'in' object data_config

Line 40: Unit ignored due to previous errors.

I guess because I have my constant associated with input port. I did not know I am not allowed to do that. Is there a better way to approach this? Thank you.

  -- Company: Quest
  -- Engineer: 
  -- Create Date:    11:11:15 1/11/2018 
  -- Design Name: 
  -- Module Name:    main - Behavioral 
  -- Project Name: 
  -- Target Devices: 
  -- Tool versions: 
  -- Description: 
  -- Dependencies: 
  -- Revision: 
  -- Revision 0.01 - File Created
  -- Additional Comments: 
  library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
     use ieee.std_logic_unsigned.all;

  entity init is

          user_clk : in  std_logic; -- 27 MHz external clk input to FPGA
          data_config : in std_logic_vector (7 downto 0);
        config_reg : std_logic_vector ( 7 downto 0);
          -- SPI 4 wires
          spi_miso : in  std_logic; -- Master in, slave out, just put high impedance since we don't read anything here, read out from LVDS
          spi_mosi : out std_logic; -- Master out, slave in, send config register values to TDC
          spi_ssn  : out std_logic; -- Slave select not, positive pulse to start, when LOW -> ready to shift of data in/out to/from device
          spi_clk  : out std_logic

  end init;

  architecture Behavioral of init is

      -- Shift register
    signal shift_reg    : std_logic_vector (7 downto 0);
     signal count     : std_logic_vector (3 downto 0) := "0000";

          --* Config register settings *--
    config_reg_settings : process (config_reg)
      type config_reg is array (0 to 3)
        of std_logic_vector (7 downto 0);
      constant data : config_reg := 
      for i in data' range loop
        data_config <= data(i);
      end loop;
     end process;
     spi_clk <= user_clk;
      -- * Master out slave in * --
     spi_process : process (user_clk)
      spi_ssn <= '1';
      if rising_edge (user_clk) then 
  --      count <= "0000";
        shift_reg <= data_config;
        spi_ssn <= '0';
        if count < "0100" then
          count <= count + "0001";
          shift_reg <= shift_reg (6 downto 0) & spi_miso; 
        end if;
      end if;
    end process;

    spi_mosi <= shift_reg(7); -- send out 8 bits at a time

  end Behavioral;
  • 2
    \$\begingroup\$ There are multiple flaws in your code: You should not use non-IEEE packages like std_logic_unsigned; use numeric_std instead. This code snippet is not complete; e.g. serialize_byte is not defined. Process config_reg_settings has no sensitivity list nor a wait statement. Shared variables are not properly supported by the Xilinx Synthesis Tool (XST). Moreover, the variable count is only used by one process. No need to declare it as shared. Use a local variable in the process; better use a signal. Process spi_mosi_mux doesn't implement a multiplexer as indicated by the label. \$\endgroup\$
    – Paebbels
    Jan 11, 2018 at 20:40
  • 1
    \$\begingroup\$ And make sure the error message and the code agree. Line 66 is blank which doesn't help. \$\endgroup\$
    – user16324
    Jan 11, 2018 at 21:27
  • \$\begingroup\$ Thank you @Paebbels for pointing out my horrible code. First time doing VHDL for me. I have fixed according to your suggestions as below. \$\endgroup\$
    – Lac
    Jan 11, 2018 at 21:45
  • 2
    \$\begingroup\$ Whether data is constant or not isn't the issue. You cannot assign to an in port; that is the issue. An in port is an external source of data into the unit; if you assign to it you destroy that incoming data. If you want data connected to data_config you can either: (a) make data_config a signal (internal to the unit, not a port) or (b) move data outside, e.g. to the testbench that instantiates this unit for testing. \$\endgroup\$
    – user16324
    Jan 11, 2018 at 22:03
  • 2
    \$\begingroup\$ And line 74 : don't add std_logic_vectors. Use the right types for the job. If these are signed numbers, make them numeric_std.signed; if they are unsigned, numeric_std_unsigned. \$\endgroup\$
    – user16324
    Jan 11, 2018 at 22:05

1 Answer 1


config_reg is of bit_vector type in your code. Change it to std_logic vector. Also you cannot drive input ports of an entity in code like that. You can write another top level VHDL file as a wrapper around this and then map those inputs to constant values using internal signals. Or convert those input ports into internal signals.


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