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1.In this circuit the R3, C1 and R6, C2 are said to act as low pass filters. The R3, C1 combo is easy to understand, however I don't get the R6, C2 configuration as they are parallel to each other, how can they act as a low pass filter? Also whats the function of D1?

2.The exit delay is achieved via C3,R7. The time constant RC determines the delay period, during which the gate input is held low. Does D2 act as some sort of protection?

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    \$\begingroup\$ I wonder what makes this alarm system "High-Performance". \$\endgroup\$ – Curd Jan 12 '18 at 13:43
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R3 and C1 are a low pass filter and are present to probably debounce the N/O contacts at the input.

D1 and C2 is a kind of controlled latch - when IC1A goes high, C2 will rapidly charge to a logic 1 level and, if IC1A's output goes low, D1 prevents C2 from being disharged i.e. C2's terminal voltage remains high and is slowly discharged via R6. In other words C2/R6 is NOT a low pass filter.

C3 is charged slowly via R7 (470 kohm) when S3-5 are open. If all of S3-5 are closed then D2 and R2 act as a reasonably rapid discharge path for C3.

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  • \$\begingroup\$ That makes sense. Thank you. I dont know why in the book they said it was low pass filter. \$\endgroup\$ – Baphomet Jan 12 '18 at 13:31
  • \$\begingroup\$ I have come across similar design in which the gate IC1A is kept low by sensors. In terms of reliability against noise and ESD which one would be better? I assume keeping the input high as it's possible to use TVS for ESD protection. \$\endgroup\$ – Baphomet Jan 12 '18 at 13:36
  • \$\begingroup\$ ESD and EMI protection/avoidance is a big subject and I'm no expert on how this can be (or should be) done on these types of alarms. \$\endgroup\$ – Andy aka Jan 12 '18 at 13:57
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R6,C2 tries to ensure some minimum alarm activation period length in case someone succeeds to reconnect the sensor chain ultrafast. C2 gets charged fast, but discharging is through R6. D1,C2,R6 is a pulse stretching circuit.

D2 lets C3 to get empty in case S7 is turned OFF. This ensures the exit period starts from the beginning.

This circuit applies several RC timing circuits where a CMOS logic gate is used as a voltage level detector. This can cause problems because around Vcc/2 input voltages the gate can behave unexpectedly (oscillations, high current consumption, even overheating if Vcc is as high as 12V)

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  • \$\begingroup\$ The value of R1 and R7 are 1m and 470k so current consumption is low. Also, by using CD4093 which is Schmidt trigger version the reliability can be increased. \$\endgroup\$ – Baphomet Jan 12 '18 at 13:49
  • \$\begingroup\$ @Baphomet R1 and R7 take microamperes, but the gate just around the treshold can take unspecified current because the whole chain of mosfets between +12V and GND is conductive. Schmitt-trigger versions fix also this. \$\endgroup\$ – user287001 Jan 12 '18 at 14:22
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If you imagine the highest frequency you can have, all the capacitors will become a short-circuit. So the signal will go straight to the ground. For the lowest frequency you can have (it's just DC current) the capacitor become an open circuit. So, the signal will go to the resistor. The diode is just a protection. The IC doesn't want to receive any current. The capacitor will get charged. You don't want the capacirot do discharge in the IC but in the rest of the circuit.

The diode D2 seems to be a protection to be sure the voltage between C3 and R7 doesn't get higher than the power source. A second tought would be appreciate here.

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