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I know that if a second order, type two PLL has only a capacitor as its loop filter, it is unstable because its phase margin would be zero. but why is it ok for a DLL to only have a capacitor as its loop filter and it doesn't need the resistor in series with the capacitor to be stable? (i.e., it doesn't need the zero) and how does this zero in PLLs improve phase noise near the PLL's bandwidth frequency?

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A PLL will measure phase and turn it into a frequency. The VCO in a PLL will perform an integrating action which adds a pole at s=0. This adds 90 degrees phase in the open loop gain. If only a capacitor is used for the loop filter, then this adds another 90 degrees phase and you may get an unstable system. A zero may need to be added to compensate for this.

\$\phi(t)=\phi(t_0)+\int_{t_0}^tf(u)du\Rightarrow\Phi(s)=\frac{F(s)}{s}\$

A DLL does not generate a frequency. There the delay element will generate a delay or phase shift derived from a fixed clock, so there is no integrating action. It just generates a delay/phase shift proportionally. So stability is still possible with only the pole from the loop filter.

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  • \$\begingroup\$ And how does this zero in PLLs improve the phase noise? @Sven B \$\endgroup\$
    – Fateme
    Commented Jan 13, 2018 at 10:28
  • \$\begingroup\$ The main reason for the zero is to compensate for the pole at s=0. But if you do that, you can increase the open loop gain (because it is more stable) which in turn will reduce noise because the feedback is stronger. \$\endgroup\$
    – Sven B
    Commented Jan 13, 2018 at 10:31

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